{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,29]],"date-time":"2025-06-29T10:10:02Z","timestamp":1751191802223,"version":"3.41.0"},"publisher-location":"Singapore","reference-count":27,"publisher":"Springer Singapore","isbn-type":[{"type":"print","value":"9789811078439"},{"type":"electronic","value":"9789811078446"}],"license":[{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018]]},"DOI":"10.1007\/978-981-10-7844-6_12","type":"book-chapter","created":{"date-parts":[[2018,1,2]],"date-time":"2018-01-02T05:42:22Z","timestamp":1514871742000},"page":"116-132","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Research of Configurable Hybrid Memory Architecture for Big Data Processing"],"prefix":"10.1007","author":[{"given":"Hongwei","family":"Zhou","sequence":"first","affiliation":[]},{"given":"Rangyu","family":"Deng","sequence":"additional","affiliation":[]},{"given":"Quanyou","family":"Feng","sequence":"additional","affiliation":[]},{"given":"Xiaoqiang","family":"Ni","sequence":"additional","affiliation":[]},{"given":"Qiang","family":"Dou","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2018,1,3]]},"reference":[{"key":"12_CR1","unstructured":"Koomey, J.: Estimating Total power consumption by servers in the U.S. and the World. Lawrence Berkeley National Laboratory, USA (2007)"},{"key":"12_CR2","unstructured":"288\u00a0Mb SIO Reduced Latency (RLDRAM II) Datasheet [DB\/OL] (2003). http:\/\/www.micron.com"},{"issue":"2","key":"12_CR3","doi-asserted-by":"publisher","first-page":"7","DOI":"10.1109\/MM.2010.38","volume":"30","author":"R Kalla","year":"2010","unstructured":"Kalla, R., Sinharoy, B., Starke, W., Floyd, M.: POWER7: IBM\u2019s next-generation server processor. IEEE Micro 30(2), 7\u201315 (2010)","journal-title":"IEEE Micro"},{"key":"12_CR4","doi-asserted-by":"crossref","unstructured":"Zhao, W., Belhaire, E., Mistral, Q., et al.: Macro-model of spin-transfer torque based magnetic tunnel junction device for hybrid magnetic\u2013CMOS design. In: IEEE International Behavioral Modeling and Simulation Workshop, pp. 40\u201343 (2006)","DOI":"10.1109\/BMAS.2006.283467"},{"key":"12_CR5","doi-asserted-by":"crossref","unstructured":"Sun, G., Dong, X., Xie, Y., Li, J., Chen, Y.: A novel architecture of the 3D stacked MRAM L2 cache for CMPs. In: High Performance Computer Architecture, pp. 239\u2013249, February 2009","DOI":"10.1109\/HPCA.2009.4798259"},{"key":"12_CR6","doi-asserted-by":"crossref","unstructured":"Hanzawa, S., Kitai, N., Osada, K., Kotabe, A., et al.: A 512\u00a0KB embedded phase change memory with 416\u00a0kB\/s write throughput at 100\u00a0uA cell write current. In: IEEE International Solid-State Circuits Conference, pp. 474\u2013616 (2007)","DOI":"10.1109\/ISSCC.2007.373500"},{"key":"12_CR7","doi-asserted-by":"crossref","unstructured":"Chung, L.: Cell design considerations for phase change memory as a universal memory. In: International Symposium on VLSI Technology, Systems and Applications, pp. 132\u2013133 (2008)","DOI":"10.1109\/VTSA.2008.4530832"},{"key":"12_CR8","doi-asserted-by":"crossref","unstructured":"Chen, Y.S., Lee, H.Y., et al.: Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity. In: Proceeding of the International Electron Devices Meeting, pp. 105\u2013108 (2009)","DOI":"10.1109\/IEDM.2009.5424411"},{"key":"12_CR9","doi-asserted-by":"crossref","unstructured":"Sheu, S.S., Chang, M.F., Lin, K.F., et al.: A 4\u00a0Mb embedded SLC resistive-RAM macro with 7.2\u00a0ns read-write random-access time and 160\u00a0ns MLC-access capability. In: Proceeding of the IEEE International Solid-State Circuit Conference, pp. 200\u2013201 (2011)","DOI":"10.1109\/ISSCC.2011.5746281"},{"key":"12_CR10","doi-asserted-by":"crossref","unstructured":"Zhou, P., Zhao, B., Yang, J., Zhang, Y.: A durable and energy efficient main memory using phase change memory technology. In: International Symposium on Computer Architecture (ISCA 2009), pp. 14\u201332, June 2009","DOI":"10.1145\/1555815.1555759"},{"issue":"1","key":"12_CR11","doi-asserted-by":"publisher","first-page":"143","DOI":"10.1109\/MM.2010.24","volume":"30","author":"BC Lee","year":"2010","unstructured":"Lee, B.C., Zhou, P., Yang, J., Zhang, Y., Zhao, B., Ipek, E., Mutlu, O., Burger, D.: Phase-change technology and the future of main memory. IEEE Micro 30(1), 143 (2010)","journal-title":"IEEE Micro"},{"key":"12_CR12","doi-asserted-by":"crossref","unstructured":"Wu, X., Li, J., Zhang, L., et al.: Design exploration of hybrid caches with disparate memory technologies. ACM Trans. Archit. Code Optim. 7(3) (2010)","DOI":"10.1145\/1880037.1880040"},{"key":"12_CR13","doi-asserted-by":"crossref","unstructured":"Wu, X., Li, J., Zhang, L., et al.: Power and performance of read-write aware hybrid caches with non-volatile memories. In: Proceeding of the Conference on Design, Automation and Test in Europe, pp. 737\u2013742 (2009)","DOI":"10.1109\/DATE.2009.5090762"},{"key":"12_CR14","doi-asserted-by":"crossref","unstructured":"Valero, A., Sahuquillo, J., petit, S., et al.: A hybrid eDRAM\/SDRAM macrocell. In: Annual IEEE\/ACM International Symposium on Microarchitecture, pp. 213\u2013221 (2009)","DOI":"10.1145\/1669112.1669140"},{"key":"12_CR15","doi-asserted-by":"crossref","unstructured":"Yu, W.S., Huang, R., Xu, S.Q., et al.: SRAM-DRAM hybrid memory with application to efficient register files in fine-grained multi-threading. In: International Symposium on Computer Architecture (ISCA 2011), pp. 247\u2013258, June 2011","DOI":"10.1145\/2024723.2000094"},{"key":"12_CR16","doi-asserted-by":"crossref","unstructured":"Caulfield, A.M., De, A., Coburn, J., et al.: Moneta: a high-performance storage array architecture for next-generation, non-volatile memories. In: Proceedings of the International Symposium on Microarchitecture, pp. 385\u2013395 (2010)","DOI":"10.1109\/MICRO.2010.33"},{"key":"12_CR17","doi-asserted-by":"crossref","unstructured":"Zhou, P., Zhao, B., Yang, J., Zhang, Y.: Energy reduction for STT-RAM using early write termination. In: Proceedings of the International Conference on Computer-Aided Design, pp. 264\u2013268 (2009)","DOI":"10.1145\/1687399.1687448"},{"key":"12_CR18","doi-asserted-by":"crossref","unstructured":"Qureshi, M.K., Franceschini, M., Lastras, L.: Improving read performance of phase change memories via write cancellation and write pausing. In: Proceedings of the International Symposium on High Performance Computer Architecture, pp. 1\u201311 (2010)","DOI":"10.1109\/HPCA.2010.5416645"},{"key":"12_CR19","unstructured":"Mogul, J.C., Argollo, E., Shah, M., Faraboschi, P.: Operating system support for NVM+DRAM hybrid main memory. In: The 12th Workshop on Hot Topics in Operating Systems (HatOS XII), pp. 18\u201320, May 2009"},{"key":"12_CR20","unstructured":"Make full use of the powerful SAP HANA memory computing platform [DB\/OL] (2015). http:\/\/www.sap.com\/china\/pc\/tech\/in-memory-computing-hana.html"},{"key":"12_CR21","unstructured":"Engineered System for Extreme Analytics [DB\/OL] (2015). https:\/\/www.oracle.com\/engineered-systems\/exalytics\/index.html"},{"key":"12_CR22","unstructured":"Ousterhout, J.: RAMCloud: Scalable High-Performance Storage Entirely in DRAM [DB\/OL]. Stanford University (2009). http:\/\/www.cs.uci.edu\/bin\/pdf\/seminarseries2011\/RAMCloud-Irvine.pdf"},{"key":"12_CR23","doi-asserted-by":"crossref","unstructured":"Huang, L., Wang, Z., Xiao, N., Wang, Y., Dou, Q.: Integrated coherence prediction: towards efficient cache coherence on NoC-based multicore architectures. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 19(3) (2014)","DOI":"10.1145\/2611756"},{"issue":"3","key":"12_CR24","first-page":"1","volume":"12","author":"C Li","year":"2015","unstructured":"Li, C., Ma, S., Chen, S., et al.: Express ring: a multi-layer and non-blocking NoC architecture. IEICE Electron. Express 12(3), 1\u201312 (2015)","journal-title":"IEICE Electron. Express"},{"key":"12_CR25","series-title":"Communications in Computer and Information Science","doi-asserted-by":"publisher","first-page":"16","DOI":"10.1007\/978-3-642-35898-2_3","volume-title":"Computer Engineering and Technology","author":"X Yan","year":"2013","unstructured":"Yan, X., Deng, R., Sun, C., Dou, Q.: MGTE: a multi-level hybrid verification platform for a 16-core processor. In: Xu, W., Xiao, L., Lu, P., Li, J., Zhang, C. (eds.) NCCET 2012. CCIS, vol. 337, pp. 16\u201326. Springer, Heidelberg (2013). https:\/\/doi.org\/10.1007\/978-3-642-35898-2_3"},{"key":"12_CR26","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"174","DOI":"10.1007\/978-3-642-03770-2_24","volume-title":"Recent Advances in Parallel Virtual Machine and Message Passing Interface","author":"DA Mall\u00f3n","year":"2009","unstructured":"Mall\u00f3n, D.A., et al.: Performance evaluation of MPI, UPC and OpenMP on multicore architectures. In: Ropo, M., Westerholm, J., Dongarra, J. (eds.) EuroPVM\/MPI 2009. LNCS, vol. 5759, pp. 174\u2013184. Springer, Heidelberg (2009). https:\/\/doi.org\/10.1007\/978-3-642-03770-2_24"},{"key":"12_CR27","unstructured":"Van der Wijngaart, R.F., Wong, P.: NAS parallel benchmarks version 2.4 [DB\/OL]. NAS Technical report: NAS-02-2007 (2002)"}],"container-title":["Communications in Computer and Information Science","Computer Engineering and Technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-10-7844-6_12","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,29]],"date-time":"2025-06-29T09:49:44Z","timestamp":1751190584000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-981-10-7844-6_12"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018]]},"ISBN":["9789811078439","9789811078446"],"references-count":27,"URL":"https:\/\/doi.org\/10.1007\/978-981-10-7844-6_12","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2018]]},"assertion":[{"value":"3 January 2018","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"NCCET","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"CCF National Conference on Computer Engineering and Technology","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Xiamen","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"China","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2017","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"16 August 2017","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"18 August 2017","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"21","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"nccet2017","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/www.nccet.cn","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}