{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,10]],"date-time":"2024-09-10T18:00:03Z","timestamp":1725991203797},"publisher-location":"Singapore","reference-count":25,"publisher":"Springer Singapore","isbn-type":[{"type":"print","value":"9789811324222"},{"type":"electronic","value":"9789811324239"}],"license":[{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018]]},"DOI":"10.1007\/978-981-13-2423-9_8","type":"book-chapter","created":{"date-parts":[[2018,9,12]],"date-time":"2018-09-12T11:37:42Z","timestamp":1536752262000},"page":"95-108","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Analytical Two-Level Near Threshold Cache Exploration for Low Power Biomedical Applications"],"prefix":"10.1007","author":[{"given":"Yun","family":"Liang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shuo","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tulika","family":"Mitra","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yajun","family":"Ha","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2018,9,13]]},"reference":[{"issue":"2","key":"8_CR1","doi-asserted-by":"publisher","first-page":"59","DOI":"10.1109\/2.982917","volume":"35","author":"T Austin","year":"2002","unstructured":"Austin, T.: Simplescalar: an infrastructure for computer system modeling. Computer 35(2), 59\u201367 (2002)","journal-title":"Computer"},{"key":"8_CR2","doi-asserted-by":"crossref","unstructured":"Brooks, D., Tiwari, V., Martonosi, M.: Wattch: a framework for architectural-level power analysis and optimizations. In: ISCA (2000)","DOI":"10.1145\/339647.339657"},{"key":"8_CR3","doi-asserted-by":"crossref","unstructured":"Calhoun, B.H., Chandrakasan, A.P.: A 256 kb subthreshold SRAM in 65 nm CMOS. In: IEEE International Solid- State Circuits Conference (2006)","DOI":"10.1109\/ISSCC.2006.1696325"},{"key":"8_CR4","unstructured":"Deb, K., Kalyanmoy, D.: Multi-Objective Optimization Using Evolutionary Algorithms. Wiley (2001)"},{"key":"8_CR5","doi-asserted-by":"crossref","unstructured":"Dreslinski, R.G., et al.: Reconfigurable energy efficient near threshold cache architectures. In: MICRO (2008)","DOI":"10.1109\/MICRO.2008.4771813"},{"key":"8_CR6","unstructured":"Edler, J., Hill, M.D.: Dinero IV trace-driven uniprocessor cache simulator. http:\/\/www.cs.wisc.edu\/~markhill\/DineroIV\/"},{"issue":"4","key":"8_CR7","doi-asserted-by":"publisher","first-page":"419","DOI":"10.1145\/1027084.1027086","volume":"9","author":"A Ghosh","year":"2004","unstructured":"Ghosh, A., Givargis, T.: Cache optimization for embedded processor cores: an analytical approach. ACM Trans. Des. Autom. Electron. Syst. 9(4), 419\u2013440 (2004)","journal-title":"ACM Trans. Des. Autom. Electron. Syst."},{"key":"8_CR8","unstructured":"Gordon-Ross, A., Vahid, F., Dutt, N.: Automatic tuning of two-level caches to embedded applications. In: DATE (2004)"},{"key":"8_CR9","doi-asserted-by":"crossref","unstructured":"Gordon-Ross, A., Vahid, F., Dutt, N.: Fast configurable-cache tuning with a unified second-level cache. In: ISLPED (2005)","DOI":"10.1145\/1077603.1077681"},{"key":"8_CR10","doi-asserted-by":"crossref","unstructured":"Hardy, D., Puaut, I.: WCET analysis of multi-level non-inclusive set-associative instruction caches. In: RTSS (2008)","DOI":"10.1109\/RTSS.2008.10"},{"issue":"1","key":"8_CR11","doi-asserted-by":"publisher","first-page":"115","DOI":"10.1109\/JSSC.2008.2007160","volume":"44","author":"J Kwong","year":"2009","unstructured":"Kwong, J.: A 65 nm sub-vt microcontroller with integrated SRAM and switched capacitor DC-DC converter. IEEE J. Solid-State Circuits 44(1), 115\u2013126 (2009)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"8_CR12","doi-asserted-by":"crossref","unstructured":"Liang, Y., Mitra, T.: Cache modeling in probabilistic execution time analysis. In: DAC, pp. 319\u2013324. ACM (2008)","DOI":"10.1145\/1391469.1391551"},{"key":"8_CR13","doi-asserted-by":"crossref","unstructured":"Liang, Y., Mitra, T.: Static analysis for fast and accurate design space exploration of caches. In: CODES+ISSS, pp. 103\u2013108. ACM (2008)","DOI":"10.1145\/1450135.1450159"},{"issue":"3","key":"8_CR14","doi-asserted-by":"publisher","first-page":"43","DOI":"10.1145\/2539036.2539039","volume":"13","author":"Y Liang","year":"2013","unstructured":"Liang, Y., Mitra, T.: An analytical approach for fast and accurate design space exploration of instruction caches. TECS 13(3), 43 (2013)","journal-title":"TECS"},{"key":"8_CR15","doi-asserted-by":"crossref","unstructured":"Nazhandali, L., et al.: Energy optimization of subthreshold-voltage sensor network processors. In: ISCA (2005)","DOI":"10.1145\/1080695.1069987"},{"key":"8_CR16","doi-asserted-by":"crossref","unstructured":"Strydis, C., Kachris, C., Gaydadjiev, G.N.: ImpBench: a novel benchmark suite for biomedical, microelectronic implants. In: International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (2008)","DOI":"10.1109\/ICSAMOS.2008.4664850"},{"key":"8_CR17","doi-asserted-by":"crossref","unstructured":"Sugumar, R.A., Abraham, S.G.: Set-associative cache simulation using generalized binomial trees. ACM Trans. Comput. Syst. 13(1) (1995)","DOI":"10.1145\/200912.200918"},{"issue":"2","key":"8_CR18","doi-asserted-by":"publisher","first-page":"128","DOI":"10.1145\/254180.254184","volume":"29","author":"RA Uhlig","year":"1997","unstructured":"Uhlig, R.A., Mudge, T.N.: Trace-driven memory simulation: a survey. ACM Comput. Surv. 29(2), 128\u2013170 (1997)","journal-title":"ACM Comput. Surv."},{"issue":"1","key":"8_CR19","doi-asserted-by":"publisher","first-page":"141","DOI":"10.1109\/JSSC.2007.908005","volume":"43","author":"N Verma","year":"2008","unstructured":"Verma, N., Chandrakasan, A.P.: A 256 kb 65 nm 8t subthreshold sram employing sense-amplifier redundancy. IEEE J. Solid-State Circuits 43(1), 141\u2013149 (2008)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"1","key":"8_CR20","doi-asserted-by":"publisher","first-page":"310","DOI":"10.1109\/JSSC.2004.837945","volume":"40","author":"A Wang","year":"2005","unstructured":"Wang, A., Chandrakasan, A.: A 180mv subthreshold fft processor using a minimum energy design methodology. IEEE J. Solid-State Circuits 40(1), 310\u2013319 (2005)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"8_CR21","doi-asserted-by":"publisher","first-page":"677","DOI":"10.1109\/4.509850","volume":"31","author":"SJE Wilton","year":"1996","unstructured":"Wilton, S.J.E., Jouppi, N.P.: CACTI an enhanced cache access and cycle time model. IEEE J. Solid-State Circuits 31, 677\u2013688 (1996)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"8_CR22","doi-asserted-by":"crossref","unstructured":"Xie, X., Liang, Y., Sun, G., Chen, D.: An efficient compiler framework for cache bypassing on GPUs. In: ICCAD, pp. 516\u2013523. IEEE (2013)","DOI":"10.1109\/ICCAD.2013.6691165"},{"key":"8_CR23","doi-asserted-by":"crossref","unstructured":"Xie, X., Liang, Y., Wang, Y., Sun, G., Wang, T.: Coordinated static and dynamic cache bypassing for GPUs. In: HPCA, pp. 76\u201388. IEEE (2015)","DOI":"10.1109\/HPCA.2015.7056023"},{"key":"8_CR24","doi-asserted-by":"crossref","unstructured":"Zhang, C., Vahid, F., Najjar, W.: A highly configurable cache architecture for embedded systems. In: ISCA (2003)","DOI":"10.1145\/859634.859635"},{"issue":"2","key":"8_CR25","doi-asserted-by":"publisher","first-page":"173","DOI":"10.1162\/106365600568202","volume":"8","author":"E Zitzler","year":"2000","unstructured":"Zitzler, E., Deb, K., Thiele, L.: Comparison of multiobjective evolutionary algorithms: empirical results. Evol. Comput. 8(2), 173\u2013195 (2000)","journal-title":"Evol. Comput."}],"container-title":["Communications in Computer and Information Science","Advanced Computer Architecture"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-13-2423-9_8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,24]],"date-time":"2019-10-24T03:28:16Z","timestamp":1571887696000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-981-13-2423-9_8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018]]},"ISBN":["9789811324222","9789811324239"],"references-count":25,"URL":"https:\/\/doi.org\/10.1007\/978-981-13-2423-9_8","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2018]]},"assertion":[{"value":"ACA","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Conference on Advanced Computer Architecture","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Changsha","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"China","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2018","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"10 August 2018","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"11 August 2018","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"12","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"aca2018","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/aca2018.tcarch.org\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}