{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,25]],"date-time":"2025-03-25T19:43:25Z","timestamp":1742931805042,"version":"3.40.3"},"publisher-location":"Singapore","reference-count":20,"publisher":"Springer Singapore","isbn-type":[{"type":"print","value":"9789811359491"},{"type":"electronic","value":"9789811359507"}],"license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019]]},"DOI":"10.1007\/978-981-13-5950-7_17","type":"book-chapter","created":{"date-parts":[[2019,1,24]],"date-time":"2019-01-24T21:31:33Z","timestamp":1548365493000},"page":"198-209","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":7,"title":["SARP: Self Aware Runtime Protection Against Integrity Attacks of Hardware Trojans"],"prefix":"10.1007","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1139-9582","authenticated-orcid":false,"given":"Krishnendu","family":"Guha","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7935-0980","authenticated-orcid":false,"given":"Debasri","family":"Saha","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4380-3172","authenticated-orcid":false,"given":"Amlan","family":"Chakrabarti","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2019,1,25]]},"reference":[{"key":"17_CR1","doi-asserted-by":"crossref","unstructured":"Defense Science Board: Task Force on High Performance Microchip Supply, February 2005. \n                    http:\/\/www.acq.osd.mil\/dsb\/reports\/ADA435563.pdf","DOI":"10.21236\/ADA435837"},{"issue":"8","key":"17_CR2","doi-asserted-by":"publisher","first-page":"1229","DOI":"10.1109\/JPROC.2014.2334493","volume":"102","author":"S Bhunia","year":"2014","unstructured":"Bhunia, S., Hsiao, M.S., Banga, M., Narasimhan, S.: Hardware Trojan attacks: threat analysis and countermeasures. Proc. IEEE 102(8), 1229\u20131247 (2014)","journal-title":"Proc. IEEE"},{"issue":"3","key":"17_CR3","doi-asserted-by":"publisher","first-page":"22","DOI":"10.1109\/MDT.2002.1003786","volume":"19","author":"S Taabatabaei","year":"2002","unstructured":"Taabatabaei, S., Ivanov, A.: Embedded timing analysis: a SoC infrastructure. IEEE Des. Test 19(3), 22\u201334 (2002)","journal-title":"IEEE Des. Test"},{"issue":"2","key":"17_CR4","doi-asserted-by":"publisher","first-page":"26","DOI":"10.1109\/MDAT.2013.2249555","volume":"30","author":"K Xiao","year":"2013","unstructured":"Xiao, K., Zhang, X., Tehranipoor, M.: A clock sweeping technique for detecting hardware Trojans impacting circuits delay. IEEE Des. Test 30(2), 26\u201334 (2013)","journal-title":"IEEE Des. Test"},{"key":"17_CR5","doi-asserted-by":"crossref","unstructured":"Askarov, A., Zhang, D., Myers, A.C.: Predictive black box mitigation of timing channels. In: Proceedings of the 17th ACM Conference on Computer and Communications Security (CCS 2010), pp. 297\u2013307. ACM, New York (2010)","DOI":"10.1145\/1866307.1866341"},{"key":"17_CR6","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"231","DOI":"10.1007\/3-540-44499-8_18","volume-title":"Cryptographic Hardware and Embedded Systems \u2014 CHES 2000","author":"J-S Coron","year":"2000","unstructured":"Coron, J.-S., Goubin, L.: On boolean and arithmetic masking against differential power analysis. In: Ko\u00e7, \u00c7.K., Paar, C. (eds.) CHES 2000. LNCS, vol. 1965, pp. 231\u2013237. Springer, Heidelberg (2000). \n                    https:\/\/doi.org\/10.1007\/3-540-44499-8_18"},{"key":"17_CR7","doi-asserted-by":"crossref","unstructured":"Jayasinghe, D., Ignjatovic, A., Parameswaran, S.: NORA: algorithmic balancing without pre-charge to thwart power analysis attacks. In: 30th International Conference on VLSI Design, pp. 167\u2013172 (2017)","DOI":"10.1109\/VLSID.2017.25"},{"key":"17_CR8","doi-asserted-by":"crossref","unstructured":"McIntyre, D., Wolf, F., Papachristou, C., Bhunia, S., Weyer, D.: Dynamic evaluation of hardware trust. In: IEEE International Workshop on Hardware Oriented Security and Trust 2009 (HOST 2009), pp. 108\u2013111 (2009)","DOI":"10.1109\/HST.2009.5224990"},{"key":"17_CR9","doi-asserted-by":"crossref","unstructured":"Beaumont, M., Hopkins, B., Newby, T.: SAFER PATH: security architecture using fragmented execution and replication for protection against Trojaned hardware. In: Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 1000\u20131005 (2012)","DOI":"10.1109\/DATE.2012.6176642"},{"key":"17_CR10","doi-asserted-by":"publisher","first-page":"499","DOI":"10.1016\/j.jare.2013.11.008","volume":"5","author":"HAM Amin","year":"2014","unstructured":"Amin, H.A.M., Alkabani, Y.: Selim: system-level protection and hardware Trojan detection using weighted voting. J. Adv. Res. 5, 499\u2013505 (2014)","journal-title":"J. Adv. Res."},{"issue":"4","key":"17_CR11","doi-asserted-by":"publisher","first-page":"461","DOI":"10.1109\/TETC.2014.2348182","volume":"2","author":"C Liu","year":"2015","unstructured":"Liu, C., Rajendran, J., Yang, C., Karri, R.: Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security driven task scheduling. IEEE Trans. Emerg. Top. Comput. 2(4), 461\u2013472 (2015)","journal-title":"IEEE Trans. Emerg. Top. Comput."},{"key":"17_CR12","doi-asserted-by":"crossref","unstructured":"Guha, K., Saha, D., Chakrabarti, A.: RTNA: securing SOC architectures from confidentiality attacks at runtime using ART1 neural networks. In: 19th International Symposium on VLSI Design and Test, pp. 1\u20136 (2015)","DOI":"10.1109\/ISVDAT.2015.7208048"},{"issue":"3","key":"17_CR13","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3014166","volume":"13","author":"K Guha","year":"2017","unstructured":"Guha, K., Saha, D., Chakrabarti, A.: Real-time SoC security against passive threats using crypsis behavior of geckos. J. Emerg. Technol. Comput. Syst. 13(3), 1\u201326 (2017). Article 41","journal-title":"J. Emerg. Technol. Comput. Syst."},{"key":"17_CR14","doi-asserted-by":"crossref","unstructured":"Guha, K., Saha, D., Chakrabarti, A.: Self aware SoC security to counteract delay inducing hardware trojans at runtime. In: 30th International Conference on VLSI Design, pp. 417\u2013422 (2017)","DOI":"10.1109\/VLSID.2017.48"},{"issue":"6","key":"17_CR15","doi-asserted-by":"publisher","first-page":"767","DOI":"10.1007\/s10836-011-5255-2","volume":"27","author":"RS Chakraborty","year":"2011","unstructured":"Chakraborty, R.S., Bhunia, S.: Security against hardware Trojan attacks using key-based design obfuscation. J. Electron. Test. 27(6), 767\u2013785 (2011)","journal-title":"J. Electron. Test."},{"issue":"11","key":"17_CR16","doi-asserted-by":"publisher","first-page":"2183","DOI":"10.1109\/TC.2012.200","volume":"62","author":"S Narasimhan","year":"2013","unstructured":"Narasimhan, S., et al.: Hardware Trojan detection by multiple-parameter side-channel analysis. IEEE Trans. Comput. 62(11), 2183\u20132195 (2013)","journal-title":"IEEE Trans. Comput."},{"issue":"12","key":"17_CR17","doi-asserted-by":"publisher","first-page":"1778","DOI":"10.1109\/TCAD.2014.2356453","volume":"33","author":"K Xiao","year":"2014","unstructured":"Xiao, K., Forte, D., Tehranipoor, M.: A novel built-in self-authentication technique to prevent inserting hardware Trojans. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12), 1778\u20131791 (2014)","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"issue":"6","key":"17_CR18","doi-asserted-by":"publisher","first-page":"947","DOI":"10.1109\/TCAD.2015.2409267","volume":"34","author":"K Huang","year":"2015","unstructured":"Huang, K., Liu, Y., Korolija, N., Carulli, J.M., Makris, Y.: Recycled IC detection based on statistical methods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(6), 947\u2013960 (2015)","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"key":"17_CR19","doi-asserted-by":"crossref","unstructured":"Sarma, S., Dutt, N., Gupta, P., Venkatasubramanian, N., Nicolau, A.: Cyber physical system on chip: a self aware MPSoC paradigm with cross-layer virtual sensing and actuation. In: Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 625\u2013628 (2015)","DOI":"10.7873\/DATE.2015.0349"},{"issue":"8","key":"17_CR20","doi-asserted-by":"publisher","first-page":"1692","DOI":"10.1109\/TIFS.2015.2422674","volume":"10","author":"X Zhai","year":"2015","unstructured":"Zhai, X., Appiah, K., Ehsan, S.: A method for detecting abnormal program behavior on embedded devices. IEEE Trans. Inf. Forensics Secur. 10(8), 1692\u20131704 (2015)","journal-title":"IEEE Trans. Inf. Forensics Secur."}],"container-title":["Communications in Computer and Information Science","VLSI Design and Test"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-13-5950-7_17","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,20]],"date-time":"2019-05-20T23:42:57Z","timestamp":1558395777000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-981-13-5950-7_17"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"ISBN":["9789811359491","9789811359507"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/978-981-13-5950-7_17","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2019]]},"assertion":[{"value":"25 January 2019","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"VDAT","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Symposium on VLSI Design and Test","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Madurai","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"India","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2018","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"28 June 2018","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"30 June 2018","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"22","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"vdat2018","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/vdat2018.tce.edu","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}