{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,25]],"date-time":"2025-03-25T14:26:59Z","timestamp":1742912819792,"version":"3.40.3"},"publisher-location":"Singapore","reference-count":15,"publisher":"Springer Singapore","isbn-type":[{"type":"print","value":"9789811359491"},{"type":"electronic","value":"9789811359507"}],"license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019]]},"DOI":"10.1007\/978-981-13-5950-7_5","type":"book-chapter","created":{"date-parts":[[2019,1,24]],"date-time":"2019-01-24T21:31:33Z","timestamp":1548365493000},"page":"49-60","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Design of High Speed 5:2 and 7:2 Compressor Using Nanomagnetic Logic"],"prefix":"10.1007","author":[{"given":"Shantanu","family":"Agarwal","sequence":"first","affiliation":[]},{"given":"G.","family":"Harish","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7805-8830","authenticated-orcid":false,"given":"S.","family":"Balamurugan","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5021-7054","authenticated-orcid":false,"given":"R.","family":"Marimuthu","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2019,1,25]]},"reference":[{"issue":"20","key":"5_CR1","doi-asserted-by":"publisher","first-page":"1568","DOI":"10.1587\/elex.9.1568","volume":"9","author":"S Balamurugan","year":"2012","unstructured":"Balamurugan, S., Ghosh, S., Atul, Marimuthu, R., Mallick, P.S.: Design of low power fixed-width multiplier with row bypassing. IEICE Electron. Express 9(20), 1568\u20131575 (2012)","journal-title":"IEICE Electron. Express"},{"key":"5_CR2","doi-asserted-by":"crossref","unstructured":"Balamurugan, S., Srirangaswamy, B., Marimuthu, R., Mallick, P.S.: FPGA design and implementation of truncated multipliers using bypassing technique. In: Proceedings of the International Conference on Advances in Computing, Communications and Informatics, pp. 1111\u20131117. ACM, Chennai (2012)","DOI":"10.1145\/2345396.2345574"},{"issue":"12","key":"5_CR3","doi-asserted-by":"publisher","first-page":"2498","DOI":"10.1109\/JPROC.2013.2252317","volume":"101","author":"Dmitri E. Nikonov","year":"2013","unstructured":"Nikonov, D.E., Young, I.A.: Overview of beyond-CMOS devices and a uniform methodology for their benchmarking. In: Proceedings of IEEE, 2498\u20132533. IEEE (2013)","journal-title":"Proceedings of the IEEE"},{"issue":"33","key":"5_CR4","doi-asserted-by":"publisher","first-page":"333001","DOI":"10.1088\/0022-3727\/47\/33\/333001","volume":"47","author":"RL Stamps","year":"2014","unstructured":"Stamps, R.L., et al.: The 2014 magnetism roadmap. J. Phys. D: Appl. Phys. 47(33), 333001 (2014)","journal-title":"J. Phys. D: Appl. Phys."},{"issue":"5","key":"5_CR5","doi-asserted-by":"publisher","first-page":"727","DOI":"10.1109\/TCAD.1987.1270318","volume":"6","author":"RL Rudell","year":"1987","unstructured":"Rudell, R.L., Sangiovanni-Vincentelli, A.: Multiple-valued minimization for PLA optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(5), 727\u2013750 (1987)","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"issue":"6","key":"5_CR6","doi-asserted-by":"publisher","first-page":"1062","DOI":"10.1109\/TCAD.1987.1270347","volume":"6","author":"RK Brayton","year":"1987","unstructured":"Brayton, R.K., Rudell, R., Sangiovanni-Vincentelli, A., Wang, A.R.: MIS: a multiple-level logic optimization system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(6), 1062\u20131081 (1987)","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"key":"5_CR7","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"24","DOI":"10.1007\/978-3-642-14295-6_5","volume-title":"Computer Aided Verification","author":"R Brayton","year":"2010","unstructured":"Brayton, R., Mishchenko, A.: ABC: an academic industrial-strength verification tool. In: Touili, T., Cook, B., Jackson, P. (eds.) CAV 2010. LNCS, vol. 6174, pp. 24\u201340. Springer, Heidelberg (2010). \n                    https:\/\/doi.org\/10.1007\/978-3-642-14295-6_5"},{"issue":"8","key":"5_CR8","doi-asserted-by":"publisher","first-page":"677","DOI":"10.1109\/TC.1986.1676819","volume":"100","author":"RE Bryant","year":"1986","unstructured":"Bryant, R.E.: Graph-based algorithms for boolean function manipulation. IEEE Trans. Comput. 100(8), 677\u2013691 (1986)","journal-title":"IEEE Trans. Comput."},{"key":"5_CR9","doi-asserted-by":"crossref","unstructured":"Amar\u00fa, L., Gaillardon, P.-E., De Micheli, G.: Majority-inverter graph: a novel data-structure and algorithms for efficient logic optimization. In: Proceedings of the 51st Annual Design Automation Conference, pp. 1\u20136. ACM, San Francisco, CA, USA (2014)","DOI":"10.1145\/2593069.2593158"},{"key":"5_CR10","doi-asserted-by":"publisher","first-page":"65","DOI":"10.1109\/JXCDC.2017.2756981","volume":"3","author":"F Riente","year":"2017","unstructured":"Riente, F., et al.: MagCAD: tool for the design of 3-D magnetic circuits. IEEE J. Explor. Solid-State Comput. Devices Circuits 3, 65\u201373 (2017)","journal-title":"IEEE J. Explor. Solid-State Comput. Devices Circuits"},{"issue":"2","key":"5_CR11","doi-asserted-by":"publisher","first-page":"108","DOI":"10.25103\/jestr.102.13","volume":"10","author":"R Marimuthu","year":"2017","unstructured":"Marimuthu, R., Mallick, P.S.: Design of efficient signed multiplier using compressors for FFT architecture. J. Eng. Sci. Technol. Rev. 10(2), 108\u2013113 (2017)","journal-title":"J. Eng. Sci. Technol. Rev."},{"key":"5_CR12","doi-asserted-by":"publisher","first-page":"1027","DOI":"10.1109\/ACCESS.2016.2636128","volume":"5","author":"R Marimuthu","year":"2017","unstructured":"Marimuthu, R., Elsie Rezinold, Y., Mallick, P.S.: Design and analysis of multiplier using approximate 15-4 compressor. IEEE Access 5, 1027\u20131036 (2017)","journal-title":"IEEE Access"},{"key":"5_CR13","doi-asserted-by":"crossref","unstructured":"Marimuthu, R., Pradeepkumar, M., Bansal, D., Balamurugan, S., Mallick, P.S.: Design of high speed and low power 15-4 compressor. In: International Conference on Communication and Signal Processing, pp. 533\u2013536. IEEE, Melmaruvathur (2013)","DOI":"10.1109\/iccsp.2013.6577111"},{"issue":"8","key":"5_CR14","doi-asserted-by":"publisher","first-page":"893","DOI":"10.3844\/ajassp.2013.893.900","volume":"10","author":"R Marimuthu","year":"2013","unstructured":"Marimuthu, R., Bansal, D., Balamurugan, S., Mallick, P.S.: Design of 8-4 and 9-4 compressors for high speed multiplication. Am. J. Appl. Sci. 10(8), 893\u2013900 (2013)","journal-title":"Am. J. Appl. Sci."},{"key":"5_CR15","doi-asserted-by":"crossref","unstructured":"Menon, R., Radhakrishnan, D.: Majority-inverter graph: high performance 5: 2 compressor architectures. In: IEE Proceedings-Circuits, Devices and System, pp. 447\u2013452. IET (2006)","DOI":"10.1049\/ip-cds:20050152"}],"container-title":["Communications in Computer and Information Science","VLSI Design and Test"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-13-5950-7_5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,20]],"date-time":"2019-05-20T23:43:38Z","timestamp":1558395818000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-981-13-5950-7_5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"ISBN":["9789811359491","9789811359507"],"references-count":15,"URL":"https:\/\/doi.org\/10.1007\/978-981-13-5950-7_5","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2019]]},"assertion":[{"value":"25 January 2019","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"VDAT","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Symposium on VLSI Design and Test","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Madurai","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"India","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2018","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"28 June 2018","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"30 June 2018","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"22","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"vdat2018","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/vdat2018.tce.edu","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}