{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T05:29:00Z","timestamp":1750310940012},"publisher-location":"Singapore","reference-count":33,"publisher":"Springer Singapore","isbn-type":[{"type":"print","value":"9789811389610"},{"type":"electronic","value":"9789811389627"}],"license":[{"start":{"date-parts":[[2019,8,15]],"date-time":"2019-08-15T00:00:00Z","timestamp":1565827200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020]]},"DOI":"10.1007\/978-981-13-8962-7_8","type":"book-chapter","created":{"date-parts":[[2019,8,14]],"date-time":"2019-08-14T07:02:58Z","timestamp":1565766178000},"page":"99-110","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["Arithmetic Circuits Using Reversible Logic: A Survey Report"],"prefix":"10.1007","author":[{"given":"Arindam","family":"Banerjee","sequence":"first","affiliation":[]},{"given":"Debesh Kumar","family":"Das","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2019,8,15]]},"reference":[{"key":"8_CR1","doi-asserted-by":"publisher","first-page":"183","DOI":"10.1147\/rd.53.0183","volume":"5","author":"R Landauer","year":"1961","unstructured":"Landauer, R.: Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 5, 183 (1961)","journal-title":"IBM J. Res. Dev."},{"issue":"6","key":"8_CR2","doi-asserted-by":"publisher","first-page":"1150","DOI":"10.1109\/JPROC.2007.895188","volume":"95","author":"DJ Castello","year":"2007","unstructured":"Castello, D.J., Forney, G.D.: Cannel coding: the road to cannel capacity. Proc. IEEE. 95(6), 1150\u20131177 (2007)","journal-title":"Proc. IEEE."},{"issue":"6","key":"8_CR3","doi-asserted-by":"publisher","first-page":"525","DOI":"10.1147\/rd.176.0525","volume":"17","author":"CH Bennett","year":"1973","unstructured":"Bennett, C.H.: Logical reversibility of computation. IBM J. Res. Dev. 17(6), 525\u2013532 (1973)","journal-title":"IBM J. Res. Dev."},{"issue":"7388","key":"8_CR4","doi-asserted-by":"publisher","first-page":"187","DOI":"10.1038\/nature10872","volume":"483","author":"A Berut","year":"2012","unstructured":"Berut, A., Arakelyan, A., Petrosyan, A., Ciliberto, S., Dillenschneider, R., Lutz, E.: Experimental verification of landauer\/\u2019s principle linking information and thermodynamics. Nature 483(7388), 187\u2013189 (2012)","journal-title":"Nature"},{"key":"8_CR5","unstructured":"Hong, S., Kim, S., Papaefthymiou, M.C., Stark, W.E.: Low power parallel multiplier design for dsp applications through co-efficient optimization. In: IEEE International Conference on ASIC\/SOC, pp. 286\u2013290 (1999)"},{"key":"8_CR6","doi-asserted-by":"crossref","unstructured":"Bulic, P., Babic, Z., Avramovic, A.: A simple pipelined logarithmic multiplier. In: IEEE International Conference on Computer Design, pp. 235\u2013240, October 2010","DOI":"10.1109\/ICCD.2010.5647767"},{"key":"8_CR7","doi-asserted-by":"crossref","unstructured":"Mrazek, V., Sarwar, S.S., Sekanina, L., Vasicek, Z., Roy, K.: Design of power-efficient approximate multipliers for approximate artificial neural networks. In: IEEE\/ACM International Conference on Computer-Aided Design, pp. 1\u20137 (2016)","DOI":"10.1145\/2966986.2967021"},{"issue":"5","key":"8_CR8","doi-asserted-by":"publisher","first-page":"1782","DOI":"10.1109\/TVLSI.2016.2643639","volume":"25","author":"Suganthi Venkatachalam","year":"2017","unstructured":"Venkatachalam, S., Ko, S.B.: Design of power and area efficient approximate multipliers. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25(5), pp. 1782\u20131786 (2017)","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"issue":"6","key":"8_CR9","doi-asserted-by":"publisher","first-page":"909","DOI":"10.1109\/4.585298","volume":"32","author":"J.-T. Yoo","year":"1997","unstructured":"Yoo, J.T., Smith, K.F., Gopalakrishnan, G.: A fast parallel squarer based on divide-and-conquer. IEEE J. Solid-State Circuits 32, 909912 (June 1997)","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"8_CR10","doi-asserted-by":"crossref","unstructured":"Deshpande, A., Draper, J.: Comparing squaring and cubing units with multipliers. In: IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 466\u2013469 (2012)","DOI":"10.1109\/MWSCAS.2012.6292058"},{"key":"8_CR11","doi-asserted-by":"crossref","unstructured":"Datla, S.R., Thornton, M.A., Matula, D.W.: A low power high performance radix-4 approximate squaring circuit. In: 20th IEEE International Conference on Application Specific Systems, Architectures and Processors (ASAP), Vol.\u00a07, pp. 91\u201397 (July 2009)","DOI":"10.1109\/ASAP.2009.35"},{"key":"8_CR12","doi-asserted-by":"crossref","unstructured":"Jayashree, H.V., Thapliyal, H., Agrawal, V.K.: Design of dedicated reversible quantum circuitry for square computation. In: Proceedings of 27th International Conference on VLSI Design, pp. 551\u2013556 (January 2014)","DOI":"10.1109\/VLSID.2014.102"},{"key":"8_CR13","doi-asserted-by":"crossref","unstructured":"Kotiyal, S., Thapliyal, H., Ranganathan, N.: Circuit for reversible quantum multiplier based on binary tree optimizing ancilla and garbage bits. In: Proceedings of 27th International Conferenceon VLSI Design, pp. 545\u2013550 (January 2014)","DOI":"10.1109\/VLSID.2014.101"},{"issue":"3","key":"8_CR14","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/2491682","volume":"9","author":"Himanshu Thapliyal","year":"2013","unstructured":"Thapliyal, H., Ranganathan, N.: Design of efficient reversible logic based binary and bcd adder circuits. ACM J. Emerging Technol. Comput. Syst. 9(3), 17:1\u201317:31 (September 2013)","journal-title":"ACM Journal on Emerging Technologies in Computing Systems"},{"issue":"7","key":"8_CR15","doi-asserted-by":"publisher","first-page":"1201","DOI":"10.1109\/TVLSI.2012.2209688","volume":"21","author":"H Thapliyal","year":"2013","unstructured":"Thapliyal, H., Ranganathan, N., Kotiyal, S.: Design of testable reversible sequential circuits. IEEE Trans. VLSI 21(7), 1201\u20131209 (2013)","journal-title":"IEEE Trans. VLSI"},{"key":"8_CR16","doi-asserted-by":"crossref","unstructured":"Thakre, A.K., Chiwande, S.S., Chafale, S.D.: Design of low power multiplier using reversible logic gate. In: Proceedings of International Conference on Green Computing Communication and Electrical Engineering (6\u20138 March 2014)","DOI":"10.1109\/ICGCCEE.2014.6922303"},{"key":"8_CR17","doi-asserted-by":"crossref","unstructured":"Madhulika, C., Nayak, V.S.P., Prasanth, C., Praveen, T.H.S.: Design of systolic array multiplier circuit using reversible logic. In: 2017 2nd IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, pp. 1670\u20131673 (2017)","DOI":"10.1109\/RTEICT.2017.8256883"},{"key":"8_CR18","doi-asserted-by":"crossref","unstructured":"Wille, R., Drechsler, R.: Towards a Design Flow for Reversible Logic. Springer (2010)","DOI":"10.1007\/978-90-481-9579-4"},{"key":"8_CR19","doi-asserted-by":"publisher","first-page":"3266","DOI":"10.1103\/PhysRevA.32.3266","volume":"32","author":"A Peres","year":"1985","unstructured":"Peres, A.: Reversible logic and quantum computers. APS Phys. Rev. A 32, 3266\u20133276 (1985)","journal-title":"APS Phys. Rev. A"},{"key":"8_CR20","unstructured":"Cuccaro, S.A., Draper, T.G., Kutin, S.A.: A new quantum ripple-carry addition circuit. \n                    arXiv:quant-ph\/0410184\n                    \n                  . (February 2008)"},{"key":"8_CR21","doi-asserted-by":"crossref","unstructured":"Thapliyal, H., Arabnia, H., Srinivas, M.: Efficient reversible logic design of bcd subtractors. Springer Trans. Comput. Sci. J. 3(LNCS 5300), 99\u2013121 (2009)","DOI":"10.1007\/978-3-642-00212-0_6"},{"key":"8_CR22","doi-asserted-by":"crossref","unstructured":"Thapliyal, H., Ranganathan, N.: A new design of the reversible subtractor circuit. In: Proceedings of the 11th IEEE International Conference on Nanotechnology (IEEE NANO), pp. 1430\u20131435 (August 2011)","DOI":"10.1109\/NANO.2011.6144350"},{"key":"8_CR23","doi-asserted-by":"crossref","unstructured":"Thapliyal, H., Srinivas, M.B.: Novel reversible multiplier architecture using reversible tsg gate. In: IEEE International Conference on Computer Systems and Applications, 8th March 2006","DOI":"10.1109\/AICCSA.2006.205074"},{"issue":"3","key":"8_CR24","doi-asserted-by":"publisher","first-page":"219","DOI":"10.1007\/BF01857727","volume":"21","author":"EF Fredkin","year":"1982","unstructured":"Fredkin, E.F., Toffoli, T.: Conservative logic. Int. J. Theor. Phys. 21(3), 219\u2013253 (1982)","journal-title":"Int. J. Theor. Phys."},{"key":"8_CR25","doi-asserted-by":"publisher","first-page":"311","DOI":"10.1142\/S0218126609005083","volume":"18","author":"M Haghparast","year":"2009","unstructured":"Haghparast, M., Jassbi, S., Navi, K., Eshghi, M.: Optimized reversible multiplier circuits. J. Circuits Syst. Comput. 18, 311\u2013323 (2009)","journal-title":"J. Circuits Syst. Comput."},{"key":"8_CR26","unstructured":"Karatsuba, A., Ofman, Y.: Multiplication of many-digital numbers by automatic computers. Doklady Akad. Nauk SSSR 145 (1963)"},{"key":"8_CR27","doi-asserted-by":"crossref","unstructured":"Offermann, S., Wille, R., Dueck, G.W., Drechsler, R.: Synthesizing multiplier in reversible logic. In: 13th IEEE Symposium on DDECS, pp. 335\u2013340 (April 2010)","DOI":"10.1109\/DDECS.2010.5491757"},{"key":"8_CR28","doi-asserted-by":"crossref","unstructured":"Axelsen, H.B., Thomsen, M.K.: Garbage-free integer multiplication with constants of the form \n                    \n                      \n                    \n                    $$2^{k}\\pm 2^{l}\\pm 1$$\n                  . In: 4th Workshop on Reversible Computation (July 2012)","DOI":"10.1007\/978-3-642-36315-3_14"},{"key":"8_CR29","doi-asserted-by":"publisher","first-page":"364","DOI":"10.1007\/978-3-642-31494-0_45","volume-title":"Progress in VLSI Design and Test","author":"P. Saravanan","year":"2012","unstructured":"Saravanan, P., Chadrasekar, P., Chandran, L., Sriram, N., Kalpana, P.: Design and implementation of efficient vedic multiplier using reversible logic. In: International Symposium on VLSI Design and Test, pp. 364\u2013366 (2012)"},{"key":"8_CR30","doi-asserted-by":"crossref","unstructured":"Banerjee, A., Das, D.K.: The design of reversible multiplier using ancient indian mathematics. In: International Symposium on Electronic Design, pp. 31\u201335 (December 2013)","DOI":"10.1109\/ISED.2013.13"},{"issue":"4","key":"8_CR31","doi-asserted-by":"publisher","first-page":"467","DOI":"10.1166\/jolpe.2015.1413","volume":"11","author":"Arindam Banerjee","year":"2015","unstructured":"Banerjee, A., Das, D.K.: The design of reversible signed multiplier using ancient indian mathematics. J. Low Power Electron. 11, 467\u2013478 (December 2015)","journal-title":"Journal of Low Power Electronics"},{"key":"8_CR32","doi-asserted-by":"crossref","unstructured":"Banerjee, A., Das, D.K.: Squaring in reversible logic using iterative structure. In: Proceedings of East West Design and Test Symposium (September 2014)","DOI":"10.1109\/EWDTS.2014.7027095"},{"key":"8_CR33","doi-asserted-by":"crossref","unstructured":"Banerjee, A., Das, D.K.: Squaring in reversible logic using zero garbage and reduced ancillary inputs. In: International Conference on VLSI Design (2015)","DOI":"10.1109\/VLSID.2016.112"}],"container-title":["Advances in Intelligent Systems and Computing","Advanced Computing and Systems for Security"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-13-8962-7_8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,14]],"date-time":"2019-08-14T07:07:22Z","timestamp":1565766442000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-981-13-8962-7_8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,8,15]]},"ISBN":["9789811389610","9789811389627"],"references-count":33,"URL":"https:\/\/doi.org\/10.1007\/978-981-13-8962-7_8","relation":{},"ISSN":["2194-5357","2194-5365"],"issn-type":[{"type":"print","value":"2194-5357"},{"type":"electronic","value":"2194-5365"}],"subject":[],"published":{"date-parts":[[2019,8,15]]},"assertion":[{"value":"15 August 2019","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}