{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,25]],"date-time":"2025-03-25T14:35:49Z","timestamp":1742913349734,"version":"3.40.3"},"publisher-location":"Singapore","reference-count":11,"publisher":"Springer Singapore","isbn-type":[{"type":"print","value":"9789813297661"},{"type":"electronic","value":"9789813297678"}],"license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019]]},"DOI":"10.1007\/978-981-32-9767-8_18","type":"book-chapter","created":{"date-parts":[[2019,8,17]],"date-time":"2019-08-17T02:02:54Z","timestamp":1566007374000},"page":"202-214","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2\u00a0V, 65\u00a0nm CMOS"],"prefix":"10.1007","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4792-7167","authenticated-orcid":false,"given":"Raviteja","family":"Kammari","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2860-4749","authenticated-orcid":false,"given":"Vijaya Sankara Rao","family":"Pasupureddi","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2019,8,18]]},"reference":[{"key":"18_CR1","doi-asserted-by":"publisher","unstructured":"Mahapatra, N.R., Tareen, A., Garimella, S.V.: Comparison and analysis of delay elements. In: The 2002 45th Midwest Symposium on Circuits and Systems, MWSCAS 2002, Tulsa, OK, USA, p. II (2002). \n                    https:\/\/doi.org\/10.1109\/MWSCAS.2002.1186901","DOI":"10.1109\/MWSCAS.2002.1186901"},{"key":"18_CR2","unstructured":"Jovanovic, G.S., Stojcev, M.K.: Linear current starved delay element. In: International Scientific Conference on Information Communication and Energy Systems and Technologies (2005)"},{"issue":"3","key":"18_CR3","doi-asserted-by":"publisher","first-page":"377","DOI":"10.1109\/4.826820","volume":"35","author":"Y Moon","year":"2000","unstructured":"Moon, Y., Choi, J., Lee, K., Jeong, D.-K., Kim, M.-K.: An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance. IEEE J. Solid-State Circ. 35(3), 377\u2013384 (2000). \n                    https:\/\/doi.org\/10.1109\/4.826820","journal-title":"IEEE J. Solid-State Circ."},{"key":"18_CR4","unstructured":"Jasielski, J., Kuta, S., Machowski, W., Ko\u0142odziejski, W.: An analog dual delay locked loop using coarse and fine programmable delay elements. In: Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013, Gdynia, pp. 185\u2013190 (2013)"},{"issue":"10","key":"18_CR5","doi-asserted-by":"publisher","first-page":"662","DOI":"10.1109\/LMWC.2009.2029752","volume":"19","author":"C Lu","year":"2009","unstructured":"Lu, C., Hsieh, H., Lu, L.: A 0.6 V low-power wide-range delay-locked loop in 0.18 \n                    \n                      \n                    \n                    $$\\upmu $$\n                  m CMOS. IEEE Microwave Wirel. Components Lett. 19(10), 662\u2013664 (2009). \n                    https:\/\/doi.org\/10.1109\/LMWC.2009.2029752","journal-title":"IEEE Microwave Wirel. Components Lett."},{"issue":"3","key":"18_CR6","doi-asserted-by":"publisher","first-page":"417","DOI":"10.1109\/4.910480","volume":"36","author":"DJ Foley","year":"2001","unstructured":"Foley, D.J., Flynn, M.P.: CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator. IEEE J. Solid-State Circ. 36(3), 417\u2013423 (2001). \n                    https:\/\/doi.org\/10.1109\/4.910480","journal-title":"IEEE J. Solid-State Circ."},{"key":"18_CR7","unstructured":"Jacob Baker, R.: CMOS Circuit Design, Layout, and Simulation, 2nd edn, pp. 596\u2013600. IEEE Press, Piscataway (2012)"},{"issue":"1","key":"18_CR8","doi-asserted-by":"publisher","first-page":"39","DOI":"10.1109\/TCSI.2017.2715899","volume":"65","author":"E Bayram","year":"2018","unstructured":"Bayram, E., Aref, A.F., Saeed, M., Negra, R.: 1.5-3.3 GHz, 0.0077 \n                    \n                      \n                    \n                    $${\\rm mm}^2$$\n                  , 7 mW all-digital delay-locked loop with dead-zone free phase detector in \n                    \n                      \n                    \n                    $$0.13~\\upmu {\\rm m}$$\n                   CMOS. IEEE Trans. Circ. Syst. I: Regul. Pap. 65(1), 39\u201350 (2018). \n                    https:\/\/doi.org\/10.1109\/TCSI.2017.2715899","journal-title":"IEEE Trans. Circ. Syst. I: Regul. Pap."},{"issue":"12","key":"18_CR9","doi-asserted-by":"publisher","first-page":"2278","DOI":"10.1109\/JSSC.2004.836345","volume":"39","author":"RB Staszewski","year":"2004","unstructured":"Staszewski, R.B., et al.: All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS. IEEE J. Solid-State Circ. 39(12), 2278\u20132291 (2004). \n                    https:\/\/doi.org\/10.1109\/JSSC.2004.836345","journal-title":"IEEE J. Solid-State Circ."},{"issue":"2","key":"18_CR10","doi-asserted-by":"publisher","first-page":"215","DOI":"10.2298\/FUEE0302215J","volume":"16","author":"Goran Jovanovic","year":"2003","unstructured":"Jovanovi\u0107, G., Stojcev, M.: Voltage controlled delay line for digital signal. Facta universitatis - Ser.: Electron. Energetics 16, 215\u2013232 (2003). \n                    https:\/\/doi.org\/10.2298\/FUEE0302215J","journal-title":"Facta universitatis - series: Electronics and Energetics"},{"issue":"10","key":"18_CR11","doi-asserted-by":"publisher","first-page":"4002","DOI":"10.1109\/TED.2017.2742358","volume":"64","author":"A Sharma","year":"2017","unstructured":"Sharma, A., Alam, N., Bulusu, A.: Effective current model for inverter-transmission gate structure and its application in circuit design. IEEE Trans. Electron Devices 64(10), 4002\u20134010 (2017). \n                    https:\/\/doi.org\/10.1109\/TED.2017.2742358","journal-title":"IEEE Trans. Electron Devices"}],"container-title":["Communications in Computer and Information Science","VLSI Design and Test"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-32-9767-8_18","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,12]],"date-time":"2019-09-12T02:04:53Z","timestamp":1568253893000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-981-32-9767-8_18"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"ISBN":["9789813297661","9789813297678"],"references-count":11,"URL":"https:\/\/doi.org\/10.1007\/978-981-32-9767-8_18","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2019]]},"assertion":[{"value":"18 August 2019","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"VDAT","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Symposium on VLSI Design and Test","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Indore","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"India","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2019","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"4 July 2019","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"6 July 2019","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"23","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"vdat2019a","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/vdat2019.iiti.ac.in\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Single-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Easychair","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"199","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"63","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"0","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"32% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"-","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"No","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}