{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,25]],"date-time":"2025-03-25T14:52:05Z","timestamp":1742914325516,"version":"3.40.3"},"publisher-location":"Singapore","reference-count":17,"publisher":"Springer Singapore","isbn-type":[{"type":"print","value":"9789813297661"},{"type":"electronic","value":"9789813297678"}],"license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019]]},"DOI":"10.1007\/978-981-32-9767-8_22","type":"book-chapter","created":{"date-parts":[[2019,8,17]],"date-time":"2019-08-17T06:02:54Z","timestamp":1566021774000},"page":"247-257","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Asynchronous Hardware Design for Floating Point Multiply-Accumulate Circuit"],"prefix":"10.1007","author":[{"given":"M.","family":"Mohamed Asan Basiri","sequence":"first","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2019,8,18]]},"reference":[{"key":"22_CR1","doi-asserted-by":"publisher","first-page":"551","DOI":"10.1016\/B978-0-7506-7444-7\/50067-4","volume-title":"Digital Signal Processing","author":"Steven W. Smith","year":"2003","unstructured":"Smith, S.W.: The Scientist and Engineers Guide to Digital Signal Processing, pp. 551\u2013566. California Technical Publishing, Poway (1997)"},{"key":"22_CR2","unstructured":"Mohamed Asan Basiri, M., Sk, N.M.: Configurable folded IIR filter design. IEEE Trans. Circ. Syst. II: Express Briefs 62(12), 1144\u20131148 (2015)"},{"key":"22_CR3","doi-asserted-by":"crossref","unstructured":"Mohamed Asan Basiri, M., Sk, N.M.: An efficient VLSI architecture for lifting based 1D\/2D-discrete wavelet transform. Microprocess. Microsyst. 47, 404\u2013418 (2016)","DOI":"10.1016\/j.micpro.2016.08.007"},{"key":"22_CR4","doi-asserted-by":"crossref","unstructured":"Mohamed Asan Basiri, M., Sk, N.M.: An efficient hardware based MAC design in digital filters with complex numbers. In: IEEE International Conference on Signal Processing and Integrated Networks (SPIN), pp. 475\u2013480 (2014)","DOI":"10.1109\/SPIN.2014.6777000"},{"issue":"10","key":"22_CR5","doi-asserted-by":"publisher","first-page":"2314","DOI":"10.1109\/JSSC.2006.881557","volume":"41","author":"S.R. Vangal","year":"2006","unstructured":"Vangal, S.R., Hoskote, Y.V., Borkar, N.Y., Alvandpour, A.: 6.2-GFlops floating-point multiply-accumulator with conditional normalization. IEEE J. Solid-State Circ. 41(10), 2314\u20132323 (2006)","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"22_CR6","doi-asserted-by":"crossref","unstructured":"Mohamed Asan Basiri, M., Sk, N.M.: An efficient hardware based higher radix floating point MAC design. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 20(1), 15:1\u201315:25 (2014)","DOI":"10.1145\/2667224"},{"key":"22_CR7","doi-asserted-by":"crossref","unstructured":"Li, G., Li, Z.: Design of a fully pipelined single-precision multiply-add-fused unit. In: IEEE 20th International Conference on VLSI Design Held Jointly with 6th International Conference on Embedded Systems (VLSID 2007), pp. 318\u2013323 (2007)","DOI":"10.1109\/VLSID.2007.64"},{"key":"22_CR8","unstructured":"Mei, X.-L.: Leading zero anticipation for latency improvement in floating-point fused multiply-add units. In: IEEE International Conference on ASIC, pp. 53\u201356 (2005)"},{"key":"22_CR9","doi-asserted-by":"crossref","unstructured":"Mohamed Asan Basiri, M., Nayak, S.C., Sk, N.M.: Multiplication acceleration through quarter precision wallace tree multiplier. In: IEEE International Conference on Signal Processing and Integrated Networks (SPIN), pp. 502\u2013505 (2014)","DOI":"10.1109\/SPIN.2014.6777005"},{"key":"22_CR10","doi-asserted-by":"crossref","unstructured":"Jones, C.M., Dlay, S.S., Naguib, R.G.: Berger check prediction for concurrent error detection in the Braun array multiplier. In: IEEE International Conference on Electronics, Circuits and Systems, pp. 81\u201384 (1996)","DOI":"10.1016\/0026-2692(96)00013-4"},{"issue":"5","key":"22_CR11","doi-asserted-by":"publisher","first-page":"8","DOI":"10.1109\/MDT.2011.71","volume":"28","author":"SM Nowick","year":"2011","unstructured":"Nowick, S.M., Singh, M.: High-performance asynchronous pipelines: an overview. IEEE Des. Test Comput. 28(5), 8\u201322 (2011)","journal-title":"IEEE Des. Test Comput."},{"key":"22_CR12","doi-asserted-by":"crossref","unstructured":"Mohamed Asan Basiri, M., Shukla, S.K.: Asynchronous hardware implementations for crypto primitives. Microprocess. Microsyst. 64, 221\u2013236 (2019)","DOI":"10.1016\/j.micpro.2018.11.002"},{"key":"22_CR13","doi-asserted-by":"crossref","unstructured":"Mohamed Asan Basiri, M., Shukla, S.K.: Low power hardware implementations for network packet processing elements. Integr. VLSI J. 62, 170\u2013181 (2018)","DOI":"10.1016\/j.vlsi.2018.02.011"},{"key":"22_CR14","unstructured":"Cortadella, J., Kondratyev, A., Lavagno, L., Lwin, K., Sotiriou, C.: From synchronous to asynchronous: an automatic approach. In: IEEE Design, Automation and Test in Europe Conference and Exhibition (2004)"},{"key":"22_CR15","unstructured":"Moreira, M., Calazans, N.: Comparing two asynchronous IC design flows. In: South Symposium on Microelectronics (2012)"},{"key":"22_CR16","doi-asserted-by":"crossref","unstructured":"Xia, Z., Ishihara, S., Hariyama, M., Kameyama, M.: Dual-rail\/single-rail hybrid logic design for high-performance asynchronous circuit. In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1\u20134 (2012)","DOI":"10.1109\/ISCAS.2012.6271954"},{"issue":"8","key":"22_CR17","doi-asserted-by":"publisher","first-page":"1210","DOI":"10.1109\/4.604077","volume":"32","author":"R Gonzalez","year":"1997","unstructured":"Gonzalez, R., Gordon, B.M., Horowitz, M.A.: Supply and threshold voltage scaling for low power CMOS. IEEE J. Solid State Circ. 32(8), 1210\u20131216 (1997)","journal-title":"IEEE J. Solid State Circ."}],"container-title":["Communications in Computer and Information Science","VLSI Design and Test"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-32-9767-8_22","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,9,25]],"date-time":"2022-09-25T20:58:49Z","timestamp":1664139529000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-981-32-9767-8_22"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"ISBN":["9789813297661","9789813297678"],"references-count":17,"URL":"https:\/\/doi.org\/10.1007\/978-981-32-9767-8_22","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2019]]},"assertion":[{"value":"18 August 2019","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"VDAT","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Symposium on VLSI Design and Test","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Indore","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"India","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2019","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"4 July 2019","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"6 July 2019","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"23","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"vdat2019a","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/vdat2019.iiti.ac.in\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Single-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Easychair","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"199","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"63","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"0","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"32% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"-","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"No","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}