{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,25]],"date-time":"2025-03-25T18:14:19Z","timestamp":1742926459170,"version":"3.40.3"},"publisher-location":"Singapore","reference-count":9,"publisher":"Springer Singapore","isbn-type":[{"type":"print","value":"9789813297661"},{"type":"electronic","value":"9789813297678"}],"license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019]]},"DOI":"10.1007\/978-981-32-9767-8_32","type":"book-chapter","created":{"date-parts":[[2019,8,17]],"date-time":"2019-08-17T02:02:54Z","timestamp":1566007374000},"page":"371-382","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["A True Single-Phase Error Masking Flip-Flop with Reduced Clock Power for Near-Threshold Designs"],"prefix":"10.1007","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1999-9056","authenticated-orcid":false,"given":"Priyamvada","family":"Sharma","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6993-2744","authenticated-orcid":false,"given":"Bishnu Prasad","family":"Das","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2019,8,18]]},"reference":[{"key":"32_CR1","doi-asserted-by":"publisher","unstructured":"Zhang, Y., et al.: iRazor: 3-transistor current-based error detection and correction in an ARM cortex-R4 processor. In: Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), pp. 160\u2013162. IEEE, San Francisco (2016). \n                    https:\/\/doi.org\/10.1109\/ISSCC.2016.7417956","DOI":"10.1109\/ISSCC.2016.7417956"},{"issue":"9","key":"32_CR2","doi-asserted-by":"publisher","first-page":"2054","DOI":"10.1109\/JSSC.2014.2328658","volume":"49","author":"I Kwon","year":"2014","unstructured":"Kwon, I., Kim, S., Fick, D., Kim, M., Chen, Y., Sylvester, D.: Razor-lite: a light-weight register for error detection by observing virtual supply rails. IEEE J. Solid-State Circuits 49(9), 2054\u20132066 (2014). \n                    https:\/\/doi.org\/10.1109\/JSSC.2014.2328658","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"12","key":"32_CR3","doi-asserted-by":"publisher","first-page":"2535","DOI":"10.1109\/TVLSI.2013.2296033","volume":"22","author":"BP Das","year":"2014","unstructured":"Das, B.P., Onodera, H.: Frequency independent warning detection sequential for dynamic voltage and frequency scaling in ASICs. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(12), 2535\u20132548 (2014). \n                    https:\/\/doi.org\/10.1109\/TVLSI.2013.2296033","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"32_CR4","doi-asserted-by":"publisher","unstructured":"Shang, X., Shan, W., Shi, L., Wan, X., Yang, J.: A 0.44V-1.1V 9-transistor transition-detector and half-path error detection technique for low power applications. In: Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 205\u2013208. IEEE, Seoul (2017). \n                    https:\/\/doi.org\/10.1109\/ASSCC.2017.8240252","DOI":"10.1109\/ASSCC.2017.8240252"},{"key":"32_CR5","doi-asserted-by":"publisher","unstructured":"Huang, C., Liu, T., Chiueh, T.: An energy-efficient resilient flip-flop circuit with built-in timing-error detection and correction. In: Proceedings of International Symposium VLSI Design, Automation Test (VLSI-DAT), pp. 1\u20134. IEEE, Hsinchu (2015). \n                    https:\/\/doi.org\/10.1109\/VLSI-DAT.2015.7114574","DOI":"10.1109\/VLSI-DAT.2015.7114574"},{"key":"32_CR6","doi-asserted-by":"publisher","first-page":"101","DOI":"10.1016\/j.vlsi.2017.11.006","volume":"61","author":"G Sannena","year":"2018","unstructured":"Sannena, G., Das, B.P.: Metastability immune and area efficient error masking flip-flop for timing error resilient designs. Integration 61, 101\u2013113 (2018). \n                    https:\/\/doi.org\/10.1016\/j.vlsi.2017.11.006","journal-title":"Integration"},{"issue":"11","key":"32_CR7","doi-asserted-by":"publisher","first-page":"2526","DOI":"10.1109\/JSSC.2014.2332532","volume":"49","author":"N Kawai","year":"2014","unstructured":"Kawai, N., et al.: A fully static topologically-compressed 21-transistor flip-flop with 75% power saving. IEEE J. Solid-State Circuits 49(11), 2526\u20132533 (2014). \n                    https:\/\/doi.org\/10.1109\/JSSC.2014.2332532","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"2","key":"32_CR8","doi-asserted-by":"publisher","first-page":"550","DOI":"10.1109\/JSSC.2018.2875089","volume":"54","author":"Y Cai","year":"2019","unstructured":"Cai, Y., Savanth, A., Prabhat, P., Myers, J., Weddell, A.S., Kazmierski, T.J.: Ultra-low power 18-transistor fully static contention-free single-phase clocked flip-flop in 65-nm CMOS. IEEE J. Solid-State Circuits 54(2), 550\u2013559 (2019). \n                    https:\/\/doi.org\/10.1109\/JSSC.2018.2875089","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"11","key":"32_CR9","doi-asserted-by":"publisher","first-page":"3033","DOI":"10.1109\/TVLSI.2017.2729884","volume":"25","author":"J Lin","year":"2017","unstructured":"Lin, J., Sheu, M., Hwang, Y., Wong, C., Tsai, M.: Low-power 19-transistor true single-phase clocking flip-flop design based on logic structure reduction schemes. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(11), 3033\u20133044 (2017). \n                    https:\/\/doi.org\/10.1109\/TVLSI.2017.2729884","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."}],"container-title":["Communications in Computer and Information Science","VLSI Design and Test"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-32-9767-8_32","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,12]],"date-time":"2019-09-12T02:06:17Z","timestamp":1568253977000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-981-32-9767-8_32"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"ISBN":["9789813297661","9789813297678"],"references-count":9,"URL":"https:\/\/doi.org\/10.1007\/978-981-32-9767-8_32","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2019]]},"assertion":[{"value":"18 August 2019","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"VDAT","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Symposium on VLSI Design and Test","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Indore","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"India","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2019","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"4 July 2019","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"6 July 2019","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"23","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"vdat2019a","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/vdat2019.iiti.ac.in\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Single-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Easychair","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"199","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"63","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"0","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"32% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"-","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"No","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}