{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T11:27:08Z","timestamp":1763724428951,"version":"3.40.3"},"publisher-location":"Singapore","reference-count":16,"publisher":"Springer Singapore","isbn-type":[{"type":"print","value":"9789813297661"},{"type":"electronic","value":"9789813297678"}],"license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019]]},"DOI":"10.1007\/978-981-32-9767-8_35","type":"book-chapter","created":{"date-parts":[[2019,8,17]],"date-time":"2019-08-17T02:02:54Z","timestamp":1566007374000},"page":"413-427","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":6,"title":["Identification of Effective Guidance Hints for Better Design Debugging by Formal Methods"],"prefix":"10.1007","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9960-0601","authenticated-orcid":false,"given":"V. S.","family":"Vineesh","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0479-9855","authenticated-orcid":false,"given":"Binod","family":"Kumar","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1833-5338","authenticated-orcid":false,"given":"Jay","family":"Adhaduk","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2019,8,18]]},"reference":[{"key":"35_CR1","unstructured":"http:\/\/www.opencores.org\/projects\/mesi_isc"},{"key":"35_CR2","doi-asserted-by":"publisher","unstructured":"Choi, H., Yun, B.W., Lee, Y.T.: Simulation strategy after model checking: experience in industrial soc design. In: Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No. PR00786), pp. 77\u201379, November 2000. \n                    https:\/\/doi.org\/10.1109\/HLDVT.2000.889563","DOI":"10.1109\/HLDVT.2000.889563"},{"key":"35_CR3","doi-asserted-by":"crossref","unstructured":"De Paula, F.M., Hu, A.J.: An effective guidance strategy for abstraction-guided simulation. In: 2007 44th ACM\/IEEE Design Automation Conference, pp. 63\u201368, June 2007","DOI":"10.1109\/DAC.2007.375126"},{"key":"35_CR4","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"389","DOI":"10.1007\/10722167_30","volume-title":"Computer Aided Verification","author":"R Fraer","year":"2000","unstructured":"Fraer, R., Kamhi, G., Ziv, B., Vardi, M.Y., Fix, L.: Prioritized traversal: efficient reachability analysis for verification and falsification. In: Emerson, E.A., Sistla, A.P. (eds.) CAV 2000. LNCS, vol. 1855, pp. 389\u2013402. Springer, Heidelberg (2000). \n                    https:\/\/doi.org\/10.1007\/10722167_30"},{"key":"35_CR5","doi-asserted-by":"publisher","unstructured":"Ganai, M.K., Aziz, A., Kuehlmann, A.: Enhancing simulation with BDDs and ATPG. In: Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361), pp. 385\u2013390, June 1999. \n                    https:\/\/doi.org\/10.1109\/DAC.1999.781346","DOI":"10.1109\/DAC.1999.781346"},{"key":"35_CR6","unstructured":"Ho, C.R., et al.: Post-silicon debug using formal verification waypoints. In: DVCon (2009)"},{"key":"35_CR7","doi-asserted-by":"publisher","unstructured":"Nalla, P.K., Gajavelly, R.K., Baumgartner, J., Mony, H., Kanzelman, R., Ivrii, A.: The art of semi-formal bug hunting. In: 2016 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1\u20138, November 2016. \n                    https:\/\/doi.org\/10.1145\/2966986.2967079","DOI":"10.1145\/2966986.2967079"},{"key":"35_CR8","doi-asserted-by":"publisher","unstructured":"Nanshi, K., Somenzi, F.: Guiding simulation with increasingly refined abstract traces. In: Proceedings of the 43rd Annual Design Automation Conference, DAC 2006, pp. 737\u2013742. ACM, New York (2006). \n                    https:\/\/doi.org\/10.1145\/1146909.1147097","DOI":"10.1145\/1146909.1147097"},{"key":"35_CR9","doi-asserted-by":"crossref","unstructured":"Papamarcos, M.S., Patel, J.H.: A low-overhead coherence solution for multiprocessors with private cache memories. In: Proceedings of the 11th Annual Symposium on Computer Architecture, Ann Arbor, USA, June 1984, pp. 348\u2013354 (1984)","DOI":"10.1145\/773453.808204"},{"key":"35_CR10","doi-asserted-by":"publisher","unstructured":"Ho, P., et al.: Smart simulation using collaborative formal and simulation engines. In: IEEE\/ACM International Conference on Computer Aided Design. ICCAD - 2000, IEEE\/ACM Digest of Technical Papers (Cat. No. 00CH37140), pp. 120\u2013126, November 2000. \n                    https:\/\/doi.org\/10.1109\/ICCAD.2000.896461","DOI":"10.1109\/ICCAD.2000.896461"},{"key":"35_CR11","doi-asserted-by":"crossref","unstructured":"Pong, F., Dubois, M.: The verification of cache coherence protocols. In: Proceedings of the Fifth Annual ACM Symposium on Parallel Algorithms and Architectures, SPAA 1993, pp. 11\u201320 (1993)","DOI":"10.1145\/165231.165233"},{"key":"35_CR12","doi-asserted-by":"publisher","unstructured":"Shyam, S., Bertacco, V.: Distance-guided hybrid verification with GUIDO. In: Proceedings of the Design Automation Test in Europe Conference, vol. 1, pp. 1\u20136 (2006). \n                    https:\/\/doi.org\/10.1109\/DATE.2006.244050","DOI":"10.1109\/DATE.2006.244050"},{"key":"35_CR13","unstructured":"Wolf, C.: Yosys open synthesis suite. \n                    http:\/\/www.clifford.at\/yosys\/"},{"key":"35_CR14","doi-asserted-by":"publisher","unstructured":"Yalagandula, P., Singhal, V., Aziz, A.: Automatic lighthouse generation for directed state space search. In: Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537), pp. 237\u2013242, March 2000. \n                    https:\/\/doi.org\/10.1109\/DATE.2000.840045","DOI":"10.1109\/DATE.2000.840045"},{"key":"35_CR15","doi-asserted-by":"publisher","unstructured":"Yang, C.H., Dill, D.L.: Validation with guided search of the state space. In: Proceedings 1998 Design and Automation Conference, 35th DAC. (Cat. No. 98CH36175), pp. 599\u2013604, June 1998. \n                    https:\/\/doi.org\/10.1145\/277044.277201","DOI":"10.1145\/277044.277201"},{"key":"35_CR16","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"376","DOI":"10.1007\/3-540-63166-6_37","volume-title":"Computer Aided Verification","author":"J Yuan","year":"1997","unstructured":"Yuan, J., Shen, J., Abraham, J., Aziz, A.: On combining formal and informal verification. In: Grumberg, O. (ed.) CAV 1997. LNCS, vol. 1254, pp. 376\u2013387. Springer, Heidelberg (1997). \n                    https:\/\/doi.org\/10.1007\/3-540-63166-6_37"}],"container-title":["Communications in Computer and Information Science","VLSI Design and Test"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-32-9767-8_35","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,12]],"date-time":"2019-09-12T02:06:28Z","timestamp":1568253988000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-981-32-9767-8_35"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"ISBN":["9789813297661","9789813297678"],"references-count":16,"URL":"https:\/\/doi.org\/10.1007\/978-981-32-9767-8_35","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2019]]},"assertion":[{"value":"18 August 2019","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"VDAT","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Symposium on VLSI Design and Test","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Indore","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"India","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2019","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"4 July 2019","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"6 July 2019","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"23","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"vdat2019a","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/vdat2019.iiti.ac.in\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Single-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Easychair","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"199","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"63","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"0","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"32% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"-","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"No","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}