{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,23]],"date-time":"2026-08-23T14:30:11Z","timestamp":1787495411009,"version":"build-2736575974"},"publisher-location":"Singapore","reference-count":30,"publisher":"Springer Nature Singapore","isbn-type":[{"value":"9789819248049","type":"print"},{"value":"9789819248056","type":"electronic"}],"license":[{"start":{"date-parts":[[2026,8,24]],"date-time":"2026-08-24T00:00:00Z","timestamp":1787529600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2026,8,24]],"date-time":"2026-08-24T00:00:00Z","timestamp":1787529600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2027]]},"DOI":"10.1007\/978-981-92-4805-6_34","type":"book-chapter","created":{"date-parts":[[2026,8,23]],"date-time":"2026-08-23T13:48:07Z","timestamp":1787492887000},"page":"515-530","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["CRAFT: Exploiting Precharge Cost Asymmetry for\u00a0Adaptive DRAM Row Buffer Management"],"prefix":"10.1007","author":[{"ORCID":"https:\/\/orcid.org\/0009-0003-1713-1867","authenticated-orcid":false,"given":"Han","family":"Xu","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-2113-0969","authenticated-orcid":false,"given":"Ziyang","family":"Liu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0006-2202-9789","authenticated-orcid":false,"given":"Weitong","family":"Wang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-5053-3110","authenticated-orcid":false,"given":"Yuyangheng","family":"Wang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0430-3669","authenticated-orcid":false,"given":"Fuxin","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2026,8,24]]},"reference":[{"key":"34_CR1","doi-asserted-by":"crossref","unstructured":"Ahmad, M., Hijaz, F., Shi, Q., Khan, O.: CRONO: a benchmark suite for multithreaded graph algorithms executing on futuristic multicores. In: 2015 IEEE International Symposium on Workload Characterization, pp. 44\u201355 (2015)","DOI":"10.1109\/IISWC.2015.11"},{"key":"34_CR2","doi-asserted-by":"crossref","unstructured":"Ausavarungnirun, R., Chang, K.K.W., Subramanian, L., Loh, G.H., Mutlu, O.: Staged memory scheduling: achieving high performance and scalability in heterogeneous systems. In: 39th International Symposium on Computer Architecture (ISCA 2012), pp. 416\u2013427. IEEE Computer Society (2012)","DOI":"10.1109\/ISCA.2012.6237036"},{"key":"34_CR3","doi-asserted-by":"crossref","unstructured":"Awasthi, M., Nellans, D.W., Sudan, K., Balasubramonian, R., Davis, A.: Handling the problems and opportunities posed by multiple on-chip memory controllers. In: Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, pp. 319\u2013330 (2010)","DOI":"10.1145\/1854273.1854314"},{"key":"34_CR4","unstructured":"Dodd, J.M.: Adaptive page management (2006). uS Patent 7,076,617"},{"key":"34_CR5","doi-asserted-by":"crossref","unstructured":"Ghasempour, M., Jaleel, A., Garside, J.D., Luj\u00e1n, M.: HAPPY: hybrid address-based page policy in DRAMs. In: Proceedings of the Second International Symposium on Memory Systems, pp. 311\u2013321 (2016)","DOI":"10.1145\/2989081.2989101"},{"key":"34_CR6","unstructured":"Gober, N., et al.: The Championship Simulator: Architectural Simulation for Education and Competition (2022)"},{"issue":"2","key":"34_CR7","doi-asserted-by":"publisher","first-page":"48","DOI":"10.1145\/3282307","volume":"62","author":"JL Hennessy","year":"2019","unstructured":"Hennessy, J.L., Patterson, D.A.: A new golden age for computer architecture. Commun. ACM 62(2), 48\u201360 (2019)","journal-title":"Commun. ACM"},{"issue":"4","key":"34_CR8","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/1186736.1186737","volume":"34","author":"JL Henning","year":"2006","unstructured":"Henning, J.L.: SPEC CPU2006 benchmark descriptions. ACM SIGARCH Comput. Architect. News 34(4), 1\u201317 (2006)","journal-title":"ACM SIGARCH Comput. Architect. News"},{"key":"34_CR9","doi-asserted-by":"crossref","unstructured":"Ipek, E., Mutlu, O., Mart\u00ednez, J.F., Caruana, R.: Self optimizing memory controllers: a reinforcement learning approach. In: Proceedings of the 35th Annual International Symposium on Computer Architecture, pp. 39\u201350 (2008)","DOI":"10.1109\/ISCA.2008.21"},{"key":"34_CR10","unstructured":"Jacob, B., Wang, D., Ng, S.: Memory systems: cache, DRAM, disk. Morgan Kaufmann (2010)"},{"key":"34_CR11","unstructured":"JEDEC Solid State Technology Association: JEDEC DDR5 SDRAM standard. JESD79-5 (2020)"},{"key":"34_CR12","doi-asserted-by":"crossref","unstructured":"Kaseridis, D., Stuecheli, J., John, L.K.: Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era. In: Proceedings of the 44th Annual IEEE\/ACM International Symposium on Microarchitecture, pp. 24\u201335 (2011)","DOI":"10.1145\/2155620.2155624"},{"key":"34_CR13","doi-asserted-by":"crossref","unstructured":"Kim, Y., Papamichael, M., Mutlu, O., Harchol-Balter, M.: Thread cluster memory scheduling: exploiting differences in memory access behavior. In: 43rd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO 2010), pp. 65\u201376. IEEE Computer Society (2010)","DOI":"10.1109\/MICRO.2010.51"},{"key":"34_CR14","doi-asserted-by":"crossref","unstructured":"Kim, Y., Seshadri, V., Lee, D., Liu, J., Mutlu, O.: A case for exploiting subarray-level parallelism (SALP) in DRAM. In: 39th International Symposium on Computer Architecture (ISCA 2012), pp. 368\u2013379. IEEE Computer Society (2012)","DOI":"10.1109\/ISCA.2012.6237032"},{"key":"34_CR15","doi-asserted-by":"crossref","unstructured":"Lee, D., Kim, Y., Seshadri, V., Liu, J., Subramanian, L., Mutlu, O.: Tiered-latency DRAM: a low latency and low cost DRAM architecture. In: 19th IEEE International Symposium on High Performance Computer Architecture (HPCA 2013), pp. 615\u2013626. IEEE Computer Society (2013)","DOI":"10.1109\/HPCA.2013.6522354"},{"issue":"1","key":"34_CR16","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/2898361","volume":"8","author":"J Leskovec","year":"2016","unstructured":"Leskovec, J., Sosi\u010d, R.: SNAP: a general-purpose network analysis and graph-mining library. ACM Trans. Intell. Syst. Technol. 8(1), 1\u201320 (2016)","journal-title":"ACM Trans. Intell. Syst. Technol."},{"issue":"2","key":"34_CR17","doi-asserted-by":"publisher","first-page":"106","DOI":"10.1109\/LCA.2020.2973991","volume":"19","author":"S Li","year":"2020","unstructured":"Li, S., Yang, Z., Reddy, D., Srivastava, A., Jacob, B.: DRAMsim3: a cycle-accurate, thermal-capable DRAM simulator. IEEE Comput. Archit. Lett. 19(2), 106\u2013109 (2020)","journal-title":"IEEE Comput. Archit. Lett."},{"key":"34_CR18","doi-asserted-by":"crossref","unstructured":"Liu, J., Jaiyen, B., Veras, R., Mutlu, O.: RAIDR: retention-aware intelligent DRAM refresh. In: 39th International Symposium on Computer Architecture (ISCA 2012), pp. 1\u201312. IEEE Computer Society (2012)","DOI":"10.1109\/ISCA.2012.6237001"},{"key":"34_CR19","doi-asserted-by":"crossref","unstructured":"Muralidhara, S.P., Subramanian, L., Mutlu, O., Kandemir, M.T., Moscibroda, T.: Reducing memory interference in multicore systems via application-aware memory channel partitioning. In: 44th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO 2011), pp. 374\u2013385. ACM (2011)","DOI":"10.1145\/2155620.2155664"},{"key":"34_CR20","doi-asserted-by":"crossref","unstructured":"Mutlu, O.: Memory scaling: a systems architecture perspective. In: 5th IEEE International Memory Workshop, pp. 21\u201325. IEEE (2013)","DOI":"10.1109\/IMW.2013.6582088"},{"key":"34_CR21","doi-asserted-by":"crossref","unstructured":"Mutlu, O., Moscibroda, T.: Stall-time fair memory access scheduling for chip multiprocessors. In: 40th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO 2007), pp. 146\u2013160. IEEE Computer Society (2007)","DOI":"10.1109\/MICRO.2007.21"},{"key":"34_CR22","doi-asserted-by":"crossref","unstructured":"Rafique, M.M., Lin, W.T., Ramanathan, A., Manohar, R.: Dympl: dynamic multi-feature page management policy using perceptron learning. In: Proceedings of the International Symposium on Memory Systems (2022)","DOI":"10.1145\/3565053.3565055"},{"key":"34_CR23","doi-asserted-by":"crossref","unstructured":"Rixner, S., Dally, W.J., Kapasi, U.J., Mattson, P.R., Owens, J.D.: Memory access scheduling. In: 27th International Symposium on Computer Architecture (ISCA 2000), pp. 128\u2013138. IEEE Computer Society (2000)","DOI":"10.1145\/339647.339668"},{"key":"34_CR24","doi-asserted-by":"crossref","unstructured":"Sherwood, T., Perelman, E., Hamerly, G., Calder, B.: Automatically characterizing large scale program behavior. In: Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 45\u201357 (2002)","DOI":"10.1145\/605397.605403"},{"key":"34_CR25","doi-asserted-by":"crossref","unstructured":"Shun, J., Blelloch, G.E.: LIGRA: a lightweight graph processing framework for shared memory. In: Proceedings of the 18th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp. 135\u2013146 (2013)","DOI":"10.1145\/2442516.2442530"},{"key":"34_CR26","doi-asserted-by":"crossref","unstructured":"Stuecheli, J., Kaseridis, D., Daly, D., Hunter, H.C., John, L.K.: The virtual write queue: coordinating DRAM and last-level cache policies. In: 37th International Symposium on Computer Architecture (ISCA 2010), pp. 72\u201382. ACM (2010)","DOI":"10.1145\/1815961.1815972"},{"key":"34_CR27","doi-asserted-by":"crossref","unstructured":"Subramanian, L., Seshadri, V., Kim, Y., Jaiyen, B., Mutlu, O.: MISE: providing performance predictability and improving fairness in shared main memory systems. In: 19th IEEE International Symposium on High Performance Computer Architecture (HPCA 2013), pp. 639\u2013650. IEEE Computer Society (2013)","DOI":"10.1109\/HPCA.2013.6522356"},{"key":"34_CR28","doi-asserted-by":"crossref","unstructured":"Udipi, A.N., Muralimanohar, N., Chatterjee, N., Balasubramonian, R., Davis, A., Jouppi, N.P.: Rethinking DRAM design and organization for energy-constrained multi-cores. In: 37th International Symposium on Computer Architecture (ISCA 2010), pp. 175\u2013186. ACM (2010)","DOI":"10.1145\/1815961.1815983"},{"issue":"1","key":"34_CR29","doi-asserted-by":"publisher","first-page":"20","DOI":"10.1145\/216585.216588","volume":"23","author":"WA Wulf","year":"1995","unstructured":"Wulf, W.A., McKee, S.A.: Hitting the memory wall: implications of the obvious. ACM SIGARCH Comput. Architect. News 23(1), 20\u201324 (1995)","journal-title":"ACM SIGARCH Comput. Architect. News"},{"key":"34_CR30","doi-asserted-by":"crossref","unstructured":"Zhang, Z., Zhu, Z., Zhang, X.: A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality. In: Proceedings of the 33rd Annual ACM\/IEEE International Symposium on Microarchitecture, pp. 32\u201341 (2000)","DOI":"10.1145\/360128.360134"}],"container-title":["Lecture Notes in Computer Science","Advanced Parallel Processing Technologies"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-92-4805-6_34","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,8,23]],"date-time":"2026-08-23T13:48:12Z","timestamp":1787492892000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-981-92-4805-6_34"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,8,24]]},"ISBN":["9789819248049","9789819248056"],"references-count":30,"URL":"https:\/\/doi.org\/10.1007\/978-981-92-4805-6_34","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,8,24]]},"assertion":[{"value":"24 August 2026","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"The authors have no competing interests to declare.","order":1,"name":"Ethics","label":"Disclosure of Interests","group":{"name":"EthicsHeading","label":"Ethics"}},{"value":"Artificial intelligence tools, if used, were used only for language organization and figure\/table polishing, and did not participate in the generation of the core ideas or technical content.","order":2,"name":"Ethics","label":"Use of Generative AI","group":{"name":"EthicsHeading","label":"Ethics"}},{"value":"APPT","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Symposium on Advanced Parallel Processing Technologies","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Brussels","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Belgium","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2026","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"27 July 2026","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"27 July 2026","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"17","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"appt2026","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/www.appt-conference.com\/2026","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}