{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T20:34:42Z","timestamp":1743107682866,"version":"3.40.3"},"publisher-location":"Singapore","reference-count":21,"publisher":"Springer Nature Singapore","isbn-type":[{"type":"print","value":"9789819708000"},{"type":"electronic","value":"9789819708017"}],"license":[{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024]]},"DOI":"10.1007\/978-981-97-0801-7_16","type":"book-chapter","created":{"date-parts":[[2024,2,29]],"date-time":"2024-02-29T08:03:04Z","timestamp":1709193784000},"page":"275-291","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A Pipelined AES and\u00a0SM4 Hardware Implementation for\u00a0Multi-tasking Virtualized Environments"],"prefix":"10.1007","author":[{"ORCID":"https:\/\/orcid.org\/0009-0001-4707-7203","authenticated-orcid":false,"given":"Yukang","family":"Xie","sequence":"first","affiliation":[]},{"given":"Hang","family":"Tu","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8979-5094","authenticated-orcid":false,"given":"Qin","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Changrong","family":"Chen","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2024,3,1]]},"reference":[{"issue":"2","key":"16_CR1","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3379444","volume":"53","author":"I Alam","year":"2020","unstructured":"Alam, I., et al.: A survey of network virtualization techniques for internet of things using SDN and NFV. ACM Comput. Surv. (CSUR) 53(2), 1\u201340 (2020). https:\/\/doi.org\/10.1145\/3379444","journal-title":"ACM Comput. Surv. (CSUR)"},{"key":"16_CR2","doi-asserted-by":"publisher","unstructured":"Bachrach, J., et al.: Chisel: constructing hardware in a Scala embedded language. In: Proceedings of the 49th Annual Design Automation Conference, DAC 2012, pp. 1216\u20131225. Association for Computing Machinery, New York (2012). https:\/\/doi.org\/10.1145\/2228360.2228584","DOI":"10.1145\/2228360.2228584"},{"key":"16_CR3","doi-asserted-by":"publisher","unstructured":"Chen, Y., et al.: Exploring the high-throughput and low-delay hardware design of SM4 on FPGA. In: 2022 19th International SoC Design Conference (ISOCC), pp. 211\u2013212 (2022). https:\/\/doi.org\/10.1109\/ISOCC56007.2022.10031393","DOI":"10.1109\/ISOCC56007.2022.10031393"},{"key":"16_CR4","doi-asserted-by":"publisher","unstructured":"Chu, J., Benaissa, M.: Low area memory-free FPGA implementation of the AES algorithm. In: 22nd International Conference on Field Programmable Logic and Applications (FPL), pp. 623\u2013626 (2012). https:\/\/doi.org\/10.1109\/FPL.2012.6339250","DOI":"10.1109\/FPL.2012.6339250"},{"issue":"3","key":"16_CR5","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1007\/s00145-021-09398-9","volume":"34","author":"C Dobraunig","year":"2021","unstructured":"Dobraunig, C., Eichlseder, M., Mendel, F., Schl\u00e4ffer, M.: Ascon v1.2: lightweight authenticated encryption and hashing. J. Cryptol. 34(3), 1\u201342 (2021). https:\/\/doi.org\/10.1007\/s00145-021-09398-9","journal-title":"J. Cryptol."},{"key":"16_CR6","doi-asserted-by":"publisher","unstructured":"Dworkin, M.J., et al.: Advanced encryption standard (AES) (2001). https:\/\/doi.org\/10.6028\/NIST.FIPS.197","DOI":"10.6028\/NIST.FIPS.197"},{"key":"16_CR7","doi-asserted-by":"publisher","unstructured":"Guan, Z., Li, Y., Shang, T., Liu, J., Sun, M., Li, Y.: Implementation of SM4 on FPGA: trade-off analysis between area and speed. In: 2018 IEEE International Conference on Intelligence and Safety for Robotics (ISR), pp. 192\u2013197 (2018). https:\/\/doi.org\/10.1109\/IISR.2018.8535613","DOI":"10.1109\/IISR.2018.8535613"},{"key":"16_CR8","doi-asserted-by":"publisher","first-page":"339","DOI":"10.1007\/s11390-019-1914-z","volume":"34","author":"CY Gui","year":"2019","unstructured":"Gui, C.Y., et al.: A survey on graph processing accelerators: challenges and opportunities. J. Comput. Sci. Technol. 34, 339\u2013371 (2019)","journal-title":"J. Comput. Sci. Technol."},{"key":"16_CR9","doi-asserted-by":"publisher","first-page":"87","DOI":"10.1016\/j.vlsi.2022.04.005","volume":"85","author":"X Guo","year":"2022","unstructured":"Guo, X., El-Hadedy, M., Mosanu, S., Wei, X., Skadron, K., Stan, M.R.: Agile-AES: Implementation of configurable AES primitive with agile design approach. Integration 85, 87\u201396 (2022)","journal-title":"Integration"},{"key":"16_CR10","doi-asserted-by":"publisher","unstructured":"Harb, S., Ahmad, M.O., Swamy, M.N.S.: A high-speed FPGA implementation of AES for large scale embedded systems and its applications. In: 2022 13th International Conference on Information and Communication Systems (ICICS), pp. 59\u201364 (2022). https:\/\/doi.org\/10.1109\/ICICS55353.2022.9811140","DOI":"10.1109\/ICICS55353.2022.9811140"},{"key":"16_CR11","unstructured":"Information technology - Security techniques - Encryption algorithms - Part 3: Block ciphers - Amendment 1: SM4. Standard, ISO\/IEC 18033\u20133:2010\/Amd 1:2021 (2021)"},{"key":"16_CR12","doi-asserted-by":"publisher","unstructured":"Kumar, T.M., Reddy, K.S., Rinaldi, S., Parameshachari, B.D., Arunachalam, K.: A low area high speed FPGA implementation of AES architecture for cryptography application. Electronics 10(16) (2021). https:\/\/doi.org\/10.3390\/electronics10162023. https:\/\/www.mdpi.com\/2079-9292\/10\/16\/2023","DOI":"10.3390\/electronics10162023"},{"key":"16_CR13","doi-asserted-by":"publisher","unstructured":"Liu, Q., Xu, Z., Yuan, Y.: A 66.1 GBPS single-pipeline AES on FPGA. In: 2013 International Conference on Field-Programmable Technology (FPT), pp. 378\u2013381 (2013). https:\/\/doi.org\/10.1109\/FPT.2013.6718392","DOI":"10.1109\/FPT.2013.6718392"},{"key":"16_CR14","doi-asserted-by":"publisher","unstructured":"Mansouri, Y., Babar, M.A.: A review of edge computing: features and resource virtualization. J. Parallel Distrib. Comput. 150, 155\u2013183 (2021). https:\/\/doi.org\/10.1016\/j.jpdc.2020.12.015. https:\/\/www.sciencedirect.com\/science\/article\/pii\/S0743731520304317","DOI":"10.1016\/j.jpdc.2020.12.015"},{"key":"16_CR15","doi-asserted-by":"publisher","unstructured":"Maximov, A., Ekdahl, P.: New circuit minimization techniques for smaller and faster AES SBoxes. IACR Trans. Crypt. Hardw. Embed. Syst. 2019(4), 91\u2013125 (2019). https:\/\/doi.org\/10.13154\/tches.v2019.i4.91-125. https:\/\/tches.iacr.org\/index.php\/TCHES\/article\/view\/8346","DOI":"10.13154\/tches.v2019.i4.91-125"},{"key":"16_CR16","doi-asserted-by":"publisher","unstructured":"Oukili, S., Bri, S.: High speed efficient advanced encryption standard implementation. In: 2017 International Symposium on Networks, Computers and Communications (ISNCC), pp. 1\u20134 (2017). https:\/\/doi.org\/10.1109\/ISNCC.2017.8071975","DOI":"10.1109\/ISNCC.2017.8071975"},{"key":"16_CR17","doi-asserted-by":"publisher","first-page":"102561","DOI":"10.1016\/j.sysarc.2022.102561","volume":"129","author":"B Peccerillo","year":"2022","unstructured":"Peccerillo, B., Mannino, M., Mondelli, A., Bartolini, S.: A survey on hardware accelerators: taxonomy, trends, challenges, and perspectives. J. Syst. Architect. 129, 102561 (2022). https:\/\/doi.org\/10.1016\/j.sysarc.2022.102561","journal-title":"J. Syst. Architect."},{"key":"16_CR18","doi-asserted-by":"publisher","unstructured":"Rautakoura, A., H\u00e4m\u00e4l\u00e4inen, T.: Does SOC hardware development become agile by saying so: a literature review and mapping study. ACM Trans. Embed. Comput. Syst. 22(3) (2023). https:\/\/doi.org\/10.1145\/3578554","DOI":"10.1145\/3578554"},{"issue":"6","key":"16_CR19","doi-asserted-by":"publisher","first-page":"344","DOI":"10.1049\/iet-cdt.2019.0179","volume":"14","author":"K Shahbazi","year":"2020","unstructured":"Shahbazi, K., Ko, S.B.: High throughput and area-efficient FPGA implementation of AES for high-traffic applications. IET Comput. Digit. Tech. 14(6), 344\u2013352 (2020)","journal-title":"IET Comput. Digit. Tech."},{"key":"16_CR20","doi-asserted-by":"publisher","unstructured":"Shang, M., Zhang, Q., Liu, Z., Xiang, J., Jing, J.: An ultra-compact hardware implementation of SMS4. In: 2014 IIAI 3rd International Conference on Advanced Applied Informatics, pp. 86\u201390 (2014). https:\/\/doi.org\/10.1109\/IIAI-AAI.2014.28","DOI":"10.1109\/IIAI-AAI.2014.28"},{"issue":"4","key":"16_CR21","doi-asserted-by":"publisher","first-page":"534","DOI":"10.1109\/TC.2019.2957355","volume":"69","author":"R Ueno","year":"2020","unstructured":"Ueno, R., et al.: High throughput\/gate AES hardware architectures based on datapath compression. IEEE Trans. Comput. 69(4), 534\u2013548 (2020). https:\/\/doi.org\/10.1109\/TC.2019.2957355","journal-title":"IEEE Trans. Comput."}],"container-title":["Lecture Notes in Computer Science","Algorithms and Architectures for Parallel Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-97-0801-7_16","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,29]],"date-time":"2024-02-29T08:12:59Z","timestamp":1709194379000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-981-97-0801-7_16"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024]]},"ISBN":["9789819708000","9789819708017"],"references-count":21,"URL":"https:\/\/doi.org\/10.1007\/978-981-97-0801-7_16","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2024]]},"assertion":[{"value":"1 March 2024","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"ICA3PP","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Algorithms and Architectures for Parallel Processing","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Tianjin","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"China","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2023","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"20 October 2023","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"22 October 2023","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"23","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"ica3pp2023","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/tjutanklab.com\/ica3pp2023\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Single-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Online submission system","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"439","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"145","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"0","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"33% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"5","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"No","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}