{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,26]],"date-time":"2025-03-26T13:38:10Z","timestamp":1742996290776,"version":"3.40.3"},"publisher-location":"Singapore","reference-count":14,"publisher":"Springer Nature Singapore","isbn-type":[{"type":"print","value":"9789819990047"},{"type":"electronic","value":"9789819990054"}],"license":[{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024]]},"DOI":"10.1007\/978-981-99-9005-4_18","type":"book-chapter","created":{"date-parts":[[2024,3,30]],"date-time":"2024-03-30T16:02:03Z","timestamp":1711814523000},"page":"141-147","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Design of Low-Power and Area-Efficient Square Root Carry Select Adder Using Binary to Excess-1 Converter (BEC)"],"prefix":"10.1007","author":[{"given":"Poh Yuin","family":"Lyn","sequence":"first","affiliation":[]},{"given":"Nor Azlin","family":"Ghazali","sequence":"additional","affiliation":[]},{"given":"Mohamed Fauzi Packeer","family":"Mohamed","sequence":"additional","affiliation":[]},{"given":"Muhammad Firdaus","family":"Akbar","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2024,3,31]]},"reference":[{"key":"18_CR1","first-page":"12006","volume":"1","author":"P Sireesha","year":"1916","unstructured":"Sireesha P, Kumar GR, Bhargavi CP, Sowjanya A (1916) Manga Rao P (2021) Retraction: design and analysis of 32 bit high speed carry select adder. J Phys Confer Ser 1:12006","journal-title":"J Phys Confer Ser"},{"issue":"12","key":"18_CR2","doi-asserted-by":"publisher","first-page":"78","DOI":"10.22161\/ijaers\/3.12.16","volume":"3","author":"G Sreekanth","year":"2016","unstructured":"Sreekanth G, Singh KJ, Sruthi NS (2016) Design of low power and area efficient carry select adder (CSLA) using verilog language. Int J Adv Eng Res Sci 3(12):78\u201382","journal-title":"Int J Adv Eng Res Sci"},{"key":"18_CR3","doi-asserted-by":"crossref","unstructured":"Nayak VSP, Ramchander N, Reddy RS, Redy THSP, Reddy MS (2016) Analysis and design of low-power reversible carry select adder using D-latch. In: IEEE international conference on recent trends in electronics, information and communication technology (RTEICT) pp 1917\u20131920","DOI":"10.1109\/RTEICT.2016.7808169"},{"issue":"5","key":"18_CR4","first-page":"470","volume":"8","author":"MD Nagulapati Giri","year":"2019","unstructured":"Nagulapati Giri MD (2019) A survey on various VLSI architectures of carry select adder. Int J Innov Technol Explor Eng 8(5):470\u2013474","journal-title":"Int J Innov Technol Explor Eng"},{"key":"18_CR5","doi-asserted-by":"publisher","first-page":"289","DOI":"10.1007\/978-981-19-2308-1_30","volume-title":"Micro and nanoelectronics devices, circuits and systems","author":"S Arunakumari","year":"2023","unstructured":"Arunakumari S, Rajasekahr K, Sunithamani S, Suresh Kumar D (2023) Carry select adder using binary excess-1 converter and ripple carry adder. In: Lenka TR, Misra D, Fu L (eds) Micro and nanoelectronics devices, circuits and systems. Springer, Singapore, pp 289\u2013294"},{"issue":"2","key":"18_CR6","doi-asserted-by":"publisher","first-page":"371","DOI":"10.1109\/TVLSI.2010.2101621","volume":"20","author":"B Ramkumar","year":"2012","unstructured":"Ramkumar B, Kittur HM (2012) Low-power and area-efficient carry select adder. IEEE Trans Very Large Scale Integr Syst 20(2):371\u2013375","journal-title":"IEEE Trans Very Large Scale Integr Syst"},{"key":"18_CR7","doi-asserted-by":"crossref","unstructured":"Prasad G, Nayak VSP, Sachin S, Kumar KL, Saikumar S (2016) Area and power efficient carry-select adder. In: IEEE international conference on recent trends in electronics, information and communication technology (RTEICT), pp 1897\u20131901","DOI":"10.1109\/RTEICT.2016.7808165"},{"key":"18_CR8","doi-asserted-by":"publisher","first-page":"317","DOI":"10.1016\/j.procs.2018.10.402","volume":"12","author":"AR Hebbar","year":"2018","unstructured":"Hebbar AR, Srivastava P, Joshi VK (2018) Design of high speed carry select adder using modified parallel prefix adder. Proced Comput Sci 12:317\u2013324","journal-title":"Proced Comput Sci"},{"issue":"2","key":"18_CR9","first-page":"2853","volume":"8","author":"P Gayathri","year":"2019","unstructured":"Gayathri P, Mohan Kumar R (2019) RTL design of efficient high-speed adders using quantum-dot cellular automatation. Int J Recent Technol Eng 8(2):2853\u20132857","journal-title":"Int J Recent Technol Eng"},{"key":"18_CR10","doi-asserted-by":"crossref","unstructured":"Abhiram T, Ashwin T, Sivaprasad B, Aakash S, Anita JP (2017) Modified carry select adder for power and area reduction. In: International conference on circuit, power and computing technologies (ICCPCT), pp 1\u20138","DOI":"10.1109\/ICCPCT.2017.8074371"},{"issue":"10","key":"18_CR11","doi-asserted-by":"publisher","first-page":"1254","DOI":"10.3390\/electronics8101129","volume":"8","author":"H You","year":"2019","unstructured":"You H, Yuan J, Tang W, Qiao S (2019) An energy and area efficient carry select adder with dual carry adder cell. Electronics 8(10):1254","journal-title":"Electronics"},{"key":"18_CR12","doi-asserted-by":"crossref","unstructured":"Anagha UP, Pramod P (2015) Power and area efficient carry select adder. In: IEEE recent advances in intelligent computational systems (RAICS), pp 17\u201320","DOI":"10.1109\/RAICS.2015.7488381"},{"key":"18_CR13","unstructured":"Srinivasareddy B, Anjularani MD (2014) Area-efficient 128-bit carry select adder architecture"},{"issue":"1","key":"18_CR14","doi-asserted-by":"publisher","first-page":"5","DOI":"10.54105\/ijvlsid.C1205.031322","volume":"2","author":"M Syed Mustafaa","year":"2022","unstructured":"Syed Mustafaa M, Sathish M, Nivedha S, Mohammed Magribatul Noora AK, Safrin Sifana T (2022) Design of carry select adder using BEC and common boolean logic. Indian J VLSI Des 2(1):5\u20139","journal-title":"Indian J VLSI Des"}],"container-title":["Lecture Notes in Electrical Engineering","Proceedings of the 12th International Conference on Robotics, Vision, Signal Processing and Power Applications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-981-99-9005-4_18","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,30]],"date-time":"2024-03-30T16:03:38Z","timestamp":1711814618000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-981-99-9005-4_18"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024]]},"ISBN":["9789819990047","9789819990054"],"references-count":14,"URL":"https:\/\/doi.org\/10.1007\/978-981-99-9005-4_18","relation":{},"ISSN":["1876-1100","1876-1119"],"issn-type":[{"type":"print","value":"1876-1100"},{"type":"electronic","value":"1876-1119"}],"subject":[],"published":{"date-parts":[[2024]]},"assertion":[{"value":"31 March 2024","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"RoViSP","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Robotics, Vision, Signal Processing and Power Applications","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2021","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"5 April 2021","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"6 April 2021","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"rovisp2021","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}