{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,22]],"date-time":"2025-03-22T08:47:45Z","timestamp":1742633265069},"reference-count":23,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[1996,11,1]],"date-time":"1996-11-01T00:00:00Z","timestamp":846806400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J VLSI Sign Process Syst Sign Image Video Technol"],"published-print":{"date-parts":[[1996,11]]},"DOI":"10.1007\/bf00925500","type":"journal-article","created":{"date-parts":[[2005,1,1]],"date-time":"2005-01-01T11:59:35Z","timestamp":1104580775000},"page":"207-220","source":"Crossref","is-referenced-by-count":11,"title":["High throughput VLSI DSP using replicated finite rings"],"prefix":"10.1007","volume":"14","author":[{"given":"Graham A.","family":"Jullien","sequence":"first","affiliation":[]},{"given":"Wenzhe","family":"Luo","sequence":"additional","affiliation":[]},{"given":"Neil M.","family":"Wigley","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[1996,11,1]]},"reference":[{"key":"BF00925500_CR1","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-662-22246-1","volume-title":"Number Theory in Science and Communication","author":"M.R. Schroeder","year":"1986","unstructured":"M.R. Schroeder,Number Theory in Science and Communication, Springer-Verlag, Berlin, 1986."},{"key":"BF00925500_CR2","doi-asserted-by":"crossref","unstructured":"S.R. Barraclough, M. Sotheran, K. Burgin, A.P. Wise, A. Vadher, W.P. Robbins, and R.M. Forsythe, \u201cThe design and implementation of the IMS A110 image and signal processor,\u201dIEEE Custom Integrated Circuits Conf., pp. 24.5.1\u201324.5.4, 1989.","DOI":"10.1109\/CICC.1989.56826"},{"key":"BF00925500_CR3","doi-asserted-by":"crossref","unstructured":"J.D. Mellott, J.C. Smith, and F.J. Taylor, \u201cThe gauss machine: A galois-enhanced quadratic residue number system systolic array,\u201dProceedings of the 11th IEEE Symposium on Computer Arithmetic, Windsor, Canada, 1993, pp. 156\u2013162.","DOI":"10.1109\/ARITH.1993.378097"},{"key":"BF00925500_CR4","doi-asserted-by":"crossref","first-page":"131","DOI":"10.1007\/BF00935210","volume":"2.3","author":"G.A. Jullien","year":"1990","unstructured":"G.A. Jullien, M. Taheri, S. Bandyopadhyay, and W.C. Miller, \u201cA low-overhead scheme for testing a bit level finite ring systolic array,\u201dJournal of VLSI Signal Processing, Vol. 2.3, pp. 131\u2013138, 1990.","journal-title":"Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology"},{"key":"BF00925500_CR5","volume-title":"Residue Number System Arithmetic: Modern Applications in Digital Signal Processing","author":"M.A. Soderstrand","year":"1986","unstructured":"M.A. Soderstrand, W.K. Jenkins, G.A. Jullien, and F.J. Taylor,Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, IEEE Press, New York, NY, 1986."},{"key":"BF00925500_CR6","doi-asserted-by":"crossref","first-page":"69","DOI":"10.1016\/S0065-2539(08)60608-3","volume":"80","author":"G.A. Jullien","year":"1991","unstructured":"G.A. Jullien, \u201cNumber theoretic techniques in digital signal processing,\u201dAdvances in Electronics and Electron Physics, Academic Press, 1991, Vol. 80, pp. 69\u2013163.","journal-title":"Advances in Electronics and Electron Physics"},{"key":"BF00925500_CR7","doi-asserted-by":"crossref","first-page":"1065","DOI":"10.1109\/12.57045","volume":"39","author":"N.M. Wigley","year":"1990","unstructured":"N.M. Wigley and G.A. Jullien, \u201cOn modulus replication for residue arithmetic computations of complex inner products,\u201dIEEE Trans. Comp., Vol. 39, pp. 1065\u20131076, Aug. 1990.","journal-title":"IEEE Trans. Comp."},{"issue":"No.1","key":"BF00925500_CR8","doi-asserted-by":"crossref","first-page":"76","DOI":"10.1109\/12.250611","volume":"43","author":"N.M. Wigley","year":"1994","unstructured":"N.M. Wigley and G.A. Jullien, \u201cLarge dynamic range computations over small finite rings,\u201dIEEE Trans. Comp., Vol. 43, No.1, pp. 76\u201386, 1994.","journal-title":"IEEE Trans. Comp."},{"key":"BF00925500_CR9","unstructured":"W.A.J. Chren, \u201cArea and latency improvements for DDS using the residue number system,\u201dProceedings of the 37th Mid-West Symp. on Circuits and Systems, Lafayette, LA Paper 22.5, 1994."},{"key":"BF00925500_CR10","doi-asserted-by":"crossref","unstructured":"Z. Wang, G.A. Jullien, and W.C. Miller, \u201cAlgorithms for length 15 and 30 discrete cosine transforms,\u201d1991 Asilomar Conference on Circuits Systems and Computers, Pacific Grove, CA, 1991, pp. 111\u2013115.","DOI":"10.1109\/ACSSC.1991.186424"},{"key":"BF00925500_CR11","unstructured":"C.E. Leiserson, Area Efficient VLSI Computation, Ph.D. Dissertation, Dept. Computer Science, Carnegie-Mellon University, Oct. 1981."},{"issue":"No. 10","key":"BF00925500_CR12","doi-asserted-by":"crossref","first-page":"899","DOI":"10.1109\/TC.1980.1675473","volume":"29","author":"G.A. Jullien","year":"1980","unstructured":"G.A. Jullien, \u201cImplementation of multiplication, modulo a prime number, with applications to number theoretic transforms,\u201dIEEE Trans. on Computers, Vol. C-29, No. 10, pp. 899\u2013905, 1980.","journal-title":"IEEE Trans. on Computers"},{"issue":"No. 12","key":"BF00925500_CR13","doi-asserted-by":"crossref","first-page":"1571","DOI":"10.1109\/31.108514","volume":"38","author":"G. Zelniker","year":"1991","unstructured":"G. Zelniker and F.J. Taylor, \u201cA reduced-complexity finite field ALU,\u201dIEEE Trans. on CAS, Vol. 38, No. 12, pp. 1571\u20131573, 1991.","journal-title":"IEEE Trans. on CAS"},{"key":"BF00925500_CR14","doi-asserted-by":"crossref","unstructured":"M.A. Bayoumi, G.A. Jullien, and W.C. Miller, \u201cA VLSI implementation of residue adders,\u201dIEEE Trans. on CAS, Vol. CAS-34, No. 3, 1987.","DOI":"10.1109\/TCS.1987.1086130"},{"key":"BF00925500_CR15","doi-asserted-by":"crossref","unstructured":"W. Luo, G.A. Jullien, N.M. Wigley, W.C. Miller, and Z. Wang, \u201cAn array processor for inner product computations using a fermat number ALU,\u201dProceedings of the 1995 Conference on Application Specific Array Processors, Strasbourg, 1995.","DOI":"10.1109\/ASAP.1995.522931"},{"key":"BF00925500_CR16","doi-asserted-by":"crossref","unstructured":"L.M. Leibowitz, \u201cA simplified binary arithmetic for the fermat number transform,\u201dIEEE Trans. Acoustics, Speech and Signal Processing, Vol. ASSP-24, No. 5, Oct. 1976.","DOI":"10.1109\/TASSP.1976.1162834"},{"key":"BF00925500_CR17","volume-title":"VLSI Array Processors","author":"S.Y. Kung","year":"1988","unstructured":"S.Y. Kung,VLSI Array Processors, Prentice-Hall, New Jersey, 1988."},{"issue":"No. 8","key":"BF00925500_CR18","doi-asserted-by":"crossref","first-page":"962","DOI":"10.1109\/12.403712","volume":"44","author":"Z. Wang","year":"1995","unstructured":"Z. Wang, G.A. Jullien, and W.C. Miller, \u201cA new design technique for column compression multipliers,\u201dIEEE Trans. on Computers, Vol. 44, No. 8, pp. 962\u2013970, 1995.","journal-title":"IEEE Trans. on Computers"},{"key":"BF00925500_CR19","unstructured":"Z. Wang, G.A. Jullien, W.C. Miller, J. Wang, and S.S. Bizzan, \u201cFast adders using enhanced multiple-output domino logic,\u201d Journal of Solid-State Circuits, (in print)."},{"key":"BF00925500_CR20","doi-asserted-by":"crossref","first-page":"225","DOI":"10.1109\/4.50308","volume":"25","author":"M. Afghahi","year":"1990","unstructured":"M. Afghahi and C. Svensson, \u201cA unified single-phase clocking scheme for VLSI systems,\u201dIEEE J. Solid-State Circuits, Vol. 25, pp. 225\u2013233, Feb. 1990.","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"No. 5","key":"BF00925500_CR21","doi-asserted-by":"crossref","first-page":"899","DOI":"10.1109\/JSSC.1987.1052831","volume":"22","author":"J. Yuan","year":"1987","unstructured":"J. Yuan, I. Karlsson, and C. Svensson, \u201cA true singlephase-clock dynamic CMOS circuit technique,\u201dIEEE J. of Solid-State Circuits, Vol. 22, No. 5, pp. 899\u2013901, Oct. 1987.","journal-title":"IEEE J. of Solid-State Circuits"},{"issue":"No. 6","key":"BF00925500_CR22","doi-asserted-by":"crossref","first-page":"723","DOI":"10.1109\/4.293119","volume":"39","author":"P. Larsson","year":"1994","unstructured":"P. Larsson and C. Svensson, \u201cImpact of clock slope on true single phase clocked (TSPC) circuits,\u201dIEEE J. of Solid-State Circuits, Vol. 39, No. 6, pp. 723\u2013726, June 1994.","journal-title":"IEEE J. of Solid-State Circuits"},{"key":"BF00925500_CR23","first-page":"29","volume-title":"Robustness of Digital CMOS Techniques with Special Emphasis on the True Signal Phase Clocking Strategy","author":"P. Larsson","year":"1993","unstructured":"P. Larsson, Robustness of Digital CMOS Techniques with Special Emphasis on the True Signal Phase Clocking Strategy, Ph.D. Dissertation, Linkoping University, Linkoping Studies in Science and Technology, Thesis No. 390, Linkoping, pp. 29\u201335, Aug. 1993."}],"container-title":["Journal of VLSI signal processing systems for signal, image and video technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF00925500.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/BF00925500\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF00925500","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,4,5]],"date-time":"2020-04-05T03:58:35Z","timestamp":1586059115000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/BF00925500"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1996,11]]},"references-count":23,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1996,11]]}},"alternative-id":["BF00925500"],"URL":"https:\/\/doi.org\/10.1007\/bf00925500","relation":{},"ISSN":["0922-5773"],"issn-type":[{"value":"0922-5773","type":"print"}],"subject":[],"published":{"date-parts":[[1996,11]]}}}