{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,12,22]],"date-time":"2024-12-22T13:40:08Z","timestamp":1734874808338,"version":"3.32.0"},"reference-count":23,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[1993,5,1]],"date-time":"1993-05-01T00:00:00Z","timestamp":736214400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[1993,5]]},"DOI":"10.1007\/bf00971645","type":"journal-article","created":{"date-parts":[[2005,1,8]],"date-time":"2005-01-08T23:11:59Z","timestamp":1105225919000},"page":"159-180","source":"Crossref","is-referenced-by-count":1,"title":["Test program synthesis for modules and chips having boundary scan"],"prefix":"10.1007","volume":"4","author":[{"given":"Jung-Cheun","family":"Lien","sequence":"first","affiliation":[]},{"given":"Melvin A.","family":"Breuer","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"issue":"no. 6","key":"CR1","doi-asserted-by":"crossref","first-page":"26","DOI":"10.1109\/MDT.1986.295048","volume":"3","author":"F. Beenker","year":"1986","unstructured":"F. Beenker, ?Macro testing: Unifying IC and board test,?IEEE Design & Test of Computers, vol. 3, no. 6, pp. 26?32, December 1986.","journal-title":"IEEE Design & Test of Computers"},{"key":"CR2","doi-asserted-by":"crossref","unstructured":"R.P. van Riessen, H.G. Kerkhoff and A. Kloppenburg, ?Design and implementation of a hierarchical testable architecture using the boundary scan standard,?Proc. European Test Conf., pp. 112?118, 1989.","DOI":"10.1109\/ETC.1989.36231"},{"key":"CR3","doi-asserted-by":"crossref","unstructured":"J. Maierhofer, ?Hierarchical self-test concept based on the JTAG standard,?Proc. Int. Test Conf., pp. 127?134, 1990.","DOI":"10.1109\/TEST.1990.114010"},{"key":"CR4","doi-asserted-by":"crossref","unstructured":"J. Leenstra and L. Spaanenburg, ?Using hierarchy in macro cell test assembly,?Proc. European Test Conf., pp. 63?70, 1989.","DOI":"10.1109\/ETC.1989.36221"},{"key":"CR5","doi-asserted-by":"crossref","unstructured":"J. Leenstra and L. Spaanenburg, ?Hierarchical test assembly for macro based VLSI design,?Proc. Int. Test Conf., pp. 520?529, 1990.","DOI":"10.1109\/TEST.1990.114063"},{"key":"CR6","doi-asserted-by":"crossref","unstructured":"F. Hapke, ?Automatic test program generation for a block orient VLSI chip design,?Proc. European Test Conf., pp. 71?75, 1989.","DOI":"10.1109\/ETC.1989.36222"},{"key":"CR7","doi-asserted-by":"crossref","unstructured":"J. Leenstra and L. Spaanenburg, ?Hierarchical test program development for scan circuit,?Proc. Int. Test Conf., pp. 375?384, 1991.","DOI":"10.1109\/TEST.1991.519697"},{"key":"CR8","doi-asserted-by":"crossref","unstructured":"B. Verhelst, ?The use of a test specification format in automatic test program generation,?Proc. European Test Conf., pp. 362?368, 1989.","DOI":"10.1109\/ETC.1989.36264"},{"key":"CR9","doi-asserted-by":"crossref","unstructured":"M.A. Breuer and J.C. Lien, ?A methodology for the design of hierarchically testable and maintainable digital systems,?Proc. 8th Digital Avionics Systems Conf., pp. 40?47, October 1988.","DOI":"10.2514\/6.1988-3859"},{"key":"CR10","unstructured":"IEEE Standard 1149-1-1990, ?IEEE standard test access port and boundary scan architecture,?IEEE Standards Board, 345 East 47th Street, New York, NY 10017, May 1989."},{"issue":"no. 4","key":"CR11","doi-asserted-by":"crossref","first-page":"56","DOI":"10.1109\/MDT.1985.294746","volume":"2","author":"M.S. Abadir","year":"1985","unstructured":"M.S. Abadir and M.A. Breuer, ?A knowledge based system for designing testable VLSI chips,?IEEE Design & Test of Computers, vol. 2, no. 4, pp. 56?68, August 1985.","journal-title":"IEEE Design & Test of Computers"},{"key":"CR12","unstructured":"E.B. Eichelberger and T.W. Williams, ?A logic design structure for LSI testability,?Proc. 14th Design Automation Conf., pp. 462?467, 1977."},{"key":"CR13","unstructured":"B. Konemann, J. Mucha and G. Zwiehoff, ?Built-in logic block observation techniques,?Proc. Int. Test Conf., pp. 37?41, 1979."},{"key":"CR14","doi-asserted-by":"crossref","first-page":"231","DOI":"10.1109\/41.19074","volume":"36","author":"J.C. Lien","year":"1989","unstructured":"J.C. Lien and M.A. Breuer, ?A universal test and maintenance controller for modules and boards,?IEEE Trans. on Industrial Electronics, vol. 36, pp. 231?240, May 1989.","journal-title":"IEEE Trans. on Industrial Electronics"},{"key":"CR15","unstructured":"J.C. Lien, ?A module maintenance controller prototype,?Technical Report CENG 90-14, Department of EE-Systems, University of Southern California, June 1990."},{"key":"CR16","doi-asserted-by":"crossref","unstructured":"K.P. Parker and S. Oresjo, ?A language for describing boundary scan devices,?Proc. Int. Test Conf., pp. 222?234, 1990.","DOI":"10.1109\/TEST.1990.114021"},{"key":"CR17","unstructured":"IEEE Standard 1076-1987, ?IEEE standard VHDL language reference,?IEEE Standards Board, 345 East 47th Street, New York, NY 10017, March 1988."},{"key":"CR18","unstructured":"J.C. Lien, ?Design of hierarchically testable and maintainable systems,? Ph.D. Dissertation, University of Southern California, August 1991."},{"key":"CR19","doi-asserted-by":"crossref","first-page":"358","DOI":"10.1109\/T-C.1974.223950","volume":"23","author":"W.H. Kautz","year":"1974","unstructured":"W.H. Kautz, ?Testing for faults in wiring networks,?IEEE Trans. on Computers, vol. C 23, pp. 358?363, April 1974.","journal-title":"IEEE Trans. on Computers"},{"key":"CR20","unstructured":"J.C. Lien and M.A. Breuer, ?Maximal diagnosis of wiring networks,?Proc. Int. Test Conf., pp. 96?105, 1991."},{"key":"CR21","unstructured":"S.C. Johnson, ?YACC: Yet another compiler-compiler,? in B.W. Kernighan and M.D. McIlroy,UNIX Program's Manual, Bell Laboratories, 7th Edition, 1978."},{"key":"CR22","unstructured":"M.E. Lesk and E. Schmidt, ?LEX: A lexical analyzer generator,? in B.W. Kernighan and M.D. McIlroy,UNIX Program's Manual, Bell Laboratories, 7th Edition, 1978."},{"key":"CR23","doi-asserted-by":"crossref","first-page":"117","DOI":"10.1007\/BF00134948","volume":"2","author":"J.C. Lien","year":"1991","unstructured":"J.C. Lien and M.A. Breuer, ?An optimal scheduling algorithm for testing interconnect using boundary scan,?Journal of Electronic Testing: Theory and Applications, vol. 2, pp. 117?130, March 1991.","journal-title":"Journal of Electronic Testing: Theory and Applications"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF00971645.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/BF00971645\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF00971645","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,22]],"date-time":"2024-12-22T13:03:31Z","timestamp":1734872611000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/BF00971645"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1993,5]]},"references-count":23,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1993,5]]}},"alternative-id":["BF00971645"],"URL":"https:\/\/doi.org\/10.1007\/bf00971645","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[1993,5]]}}}