{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,12,22]],"date-time":"2024-12-22T16:40:12Z","timestamp":1734885612624,"version":"3.32.0"},"reference-count":33,"publisher":"Springer Science and Business Media LLC","issue":"1-2","license":[{"start":{"date-parts":[[1995,8,1]],"date-time":"1995-08-01T00:00:00Z","timestamp":807235200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[1995,8]]},"DOI":"10.1007\/bf00993311","type":"journal-article","created":{"date-parts":[[2005,1,14]],"date-time":"2005-01-14T18:06:31Z","timestamp":1105725991000},"page":"7-23","source":"Crossref","is-referenced-by-count":3,"title":["Partial scan and symbolic test at the register-transfer level"],"prefix":"10.1007","volume":"7","author":[{"given":"Johannes","family":"Steensma","sequence":"first","affiliation":[]},{"given":"Francky","family":"Catthoor","sequence":"additional","affiliation":[]},{"given":"Hugo","family":"De Man","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"CR1","unstructured":"E. Trischler, ?Incomplete Scan Path with an Automatic Test Generation Approach,?Proc. International Test Conference, pp. 153?162, November 1980."},{"key":"CR2","doi-asserted-by":"crossref","unstructured":"V. Chickermane and J.H. Patel, ?An Optimization Based Approach to the Partial Scan Design Problem?,Proc. International Test Conference, pp. 377?386, September 1990.","DOI":"10.1109\/TEST.1990.114045"},{"key":"CR3","unstructured":"V.D. Agrawal, K.-T. Cheng, D.D. Johnson, and T. Lin, ?A Complete Solution to the Partial Scan Problem,?Proc. International Test Conference, pp. 44?51, September 1987."},{"key":"CR4","doi-asserted-by":"crossref","unstructured":"H.-K.T. Ma, S. Devadas, A.R. Newton, and A. Sangiovanni-Vincentelli, ?An Incomplete Scan Design Approach to Test Generation for Sequential Machines,?Proc. International Test Conference, pp. 730?734, September 1988.","DOI":"10.1109\/TEST.1988.207858"},{"issue":"No. 4","key":"CR5","doi-asserted-by":"crossref","first-page":"544","DOI":"10.1109\/12.54847","volume":"39","author":"K.-T. Cheng","year":"1990","unstructured":"K.-T. Cheng and V.D. Agrawal, ?A Partial Scan Method for Sequential Circuits with Feedbacks,?IEEE Transactions on Computers, Vol. 39, No. 4, pp. 544?548, April 1990.","journal-title":"IEEE Transactions on Computers"},{"issue":"No. 4","key":"CR6","doi-asserted-by":"crossref","first-page":"538","DOI":"10.1109\/12.54846","volume":"39","author":"R. Gupta","year":"1990","unstructured":"R. Gupta, R. Gupta, and M.A. Breuer, ?The BALLAST Methodology for Structured Partial Scan Design,?IEEE Transactions on Computers, Vol. 39, No. 4, pp. 538?544, April 1990.","journal-title":"IEEE Transactions on Computers"},{"issue":"No. 2","key":"CR7","doi-asserted-by":"crossref","first-page":"163","DOI":"10.1007\/BF00137392","volume":"1","author":"A. Kunzman","year":"1990","unstructured":"A. Kunzman and H.-J. Wunderlich ?An Analytical Approach to the Partial Scan Problem,?Journal of Electronic Testing: Theory and Applications, Vol. 1, No. 2, pp. 163?174, May 1990.","journal-title":"Journal of Electronic Testing: Theory and Applications"},{"key":"CR8","doi-asserted-by":"crossref","unstructured":"S. Bhawmik, C.J. Lin, K.-T. Cheng, and V.D. Agrawal, ?PASCANT: A Partial Scan and Test Generation System,?Proc. IEEE Custom Integrated Circuits Conference, pp. 17.3.1?17.3.4, 1991.","DOI":"10.1109\/CICC.1991.163995"},{"key":"CR9","unstructured":"S. Park and S.B. Akers, ?A Graph Theoretic Approach to Partial Scan Design by K-Cycle Elimination,?Proc. International Test conference, pp. 303?311, November 1992."},{"key":"CR10","doi-asserted-by":"crossref","unstructured":"S. Chakradhar, A. Balakrishnan, and V.D. Agrawal, ?An exact algorithm for selecting partial scan flip-flops,?Proc. 31st Design Automation Conference, pp. 81?86, June 1994.","DOI":"10.1145\/196244.196285"},{"key":"CR11","doi-asserted-by":"crossref","unstructured":"T.-C. Lee, N.K. Jha, and W.H. Wolf, ?A Conditional Resource Sharing Method for Behavioral Synthesis of Highly Testable Data Paths,?Proc. International Test Conference, pp. 745?753, October 1993.","DOI":"10.1109\/TEST.1993.470628"},{"key":"CR12","doi-asserted-by":"crossref","unstructured":"S. Dey, M. Potkonjak, and R.K. Roy, ?Exploiting Hardware Sharing in High-Level Synthesis for Partial Scan Optimization,?Proc. International Conference on Computer-Aided Design, pp 20?25, November 1993.","DOI":"10.1109\/ICCAD.1993.580025"},{"key":"CR13","doi-asserted-by":"crossref","unstructured":"C.H. Chen and D.G. Saab, ?Behavioral Synthesis for Testability,?Proc. International Conference on Computer-Aided Design, pp. 612?615, November 1992.","DOI":"10.1109\/ICCAD.1992.279304"},{"issue":"No. 1","key":"CR14","doi-asserted-by":"crossref","first-page":"43","DOI":"10.1007\/BF00971939","volume":"4","author":"J. Steensma","year":"1993","unstructured":"J. Steensma, W. Geurts, F. Catthoor, and H. De Mum, ?Testability Analysis in High Level Data Path Synthesis,?Journal of Electronic Testing: Theory and Applications Vol. 4, No. 1, pp. 43?56, February 1993.","journal-title":"Journal of Electronic Testing: Theory and Applications"},{"key":"CR15","unstructured":"J. Steensma, F. Catthoor, and H. De Man, ?Test of High Throughput Data Paths using Symbolic Controllability and Observability Descriptions,? 6th Workshop On New Directions For Testing, Montreal Canada, pp. 67?76, May 21?22, 1992."},{"issue":"No. 3","key":"CR16","doi-asserted-by":"crossref","first-page":"720","DOI":"10.1109\/4.102666","volume":"25","author":"E. Blokken","year":"1990","unstructured":"E. Blokken, H. De Keulenaer, F. Catthoor, and H. De Man, ?A Flexible Module Library for Custom DSP Applications in a Multi-processor Environment,?IEEE Journal of Solid State Circuits, Vol. 25, No. 3, pp. 720?729, June 1990.","journal-title":"IEEE Journal of Solid State Circuits"},{"issue":"No. 2","key":"CR17","doi-asserted-by":"crossref","first-page":"146","DOI":"10.1137\/0201010","volume":"2","author":"R. Tarjan","year":"1972","unstructured":"R. Tarjan, ?Depth-First Search and Linear Graph Algorithms,?SIAM J. Comput. Vol. 2, No. 2, pp. 146?160, June 1972.","journal-title":"SIAM J. Comput."},{"key":"CR18","doi-asserted-by":"crossref","unstructured":"S. Note, W. Geurts, F. Catthoor, and H. De Man, ?Cathedral III: Architecture Driven High-Level Synthesis for High Throughput DSP Applications,?Proc. 28th Design Automation Conference, pp. 597?602, June 1991.","DOI":"10.1145\/127601.127739"},{"key":"CR19","doi-asserted-by":"crossref","unstructured":"B.T. Murray and J.P. Hayes, ?Hierarchical Test Generation Using Precomputed Tests for Modules,?Proc. International Test Conference, pp. 221?229, September 1988.","DOI":"10.1109\/TEST.1988.207806"},{"issue":"No. 2","key":"CR20","doi-asserted-by":"crossref","first-page":"421","DOI":"10.1109\/4.1002","volume":"23","author":"S. Freeman","year":"1988","unstructured":"S. Freeman, ?Test Generation for Data-Path Logic: The F-Path Method,?IEEE Journal of Solid-State Circuits, Vol. 23, No. 2, pp. 421?427, April 1988.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"CR21","doi-asserted-by":"crossref","unstructured":"P.N. Anirudhan and P.R. Menon, ?Symbolic Test Generation for Hierarchical Modeled Digital Systems,?Proc. International Test Conference, pp. 461?469, August 1989.","DOI":"10.1109\/TEST.1989.82329"},{"key":"CR22","unstructured":"J. Steensma, F. Catthoor, and H. De Man, ?Modeling Delay in Symbolic Test for Data Paths with Partial Scan,?Proc. European Test Conference pp. 253?454, April 1993."},{"key":"CR23","doi-asserted-by":"crossref","first-page":"18","DOI":"10.1109\/54.19132","volume":"6","author":"F. Catthoor","year":"1989","unstructured":"F. Catthoor, J. van Sas, L. Inze, and H. De Man, ?A Test Strategy for Multiprocessor Architectures,?IEEE Design and Test of Computers Vol. 6, pp. 18?34, April 1989.","journal-title":"IEEE Design and Test of Computers"},{"key":"CR24","unstructured":"H. Hofest\u00e4dt and M. Gerner, ?Qualitative Testability Analysis and Hierarchial Test Pattern Generation: A New approach to Design for Testability,?Proc. International Test Conference, pp. 538?546, September 1987."},{"key":"CR25","doi-asserted-by":"crossref","unstructured":"J. Steensma, F. Catthoor, and H. De Man, ?Partial Scan at the Register-Transfer Level,?Proc. International Test Conference, pp. 488?497, October 1993.","DOI":"10.1109\/TEST.1993.470662"},{"key":"CR26","doi-asserted-by":"crossref","unstructured":"F. Beenker, R. Dekker, R. Stants and M. van der Star, ?A Testability Strategy for Silicon Compilers,?Proc. International Test Conference, pp. 660?669, August 1989.","DOI":"10.1109\/TEST.1989.82353"},{"issue":"No. 7","key":"CR27","doi-asserted-by":"crossref","first-page":"444","DOI":"10.1016\/0141-9331(90)90023-O","volume":"14","author":"J. Sas van","year":"1990","unstructured":"J. van Sas, F. Catthoor, L. Inz\u00e9, and H. De Man, ?Testability Strategy and Test Pattern Generation for Register Files and Customized Memories,?Microprocessors and Microsystems, Vol. 14, No. 7, pp. 444?456, September, 1990.","journal-title":"Microprocessors and Microsystems"},{"key":"CR28","unstructured":"S. Oostdijk, F. Beenker, and L. Thijssen, ?A Model for Test-Time Reduction of Scan Testable Circuits,?Proc. European Test Conference, pp. 243?252, April 1991."},{"key":"CR29","doi-asserted-by":"crossref","unstructured":"S. Narayanan, C. Njinda, and M.A. Breuer, ?Optimal Sequencing of Scan Registers,?Proc. International Test Conference, paper 15.2, pp. 293?302, September 1992.","DOI":"10.1109\/TEST.1992.527836"},{"issue":"No. 9","key":"CR30","doi-asserted-by":"crossref","first-page":"1121","DOI":"10.1109\/12.241600","volume":"42","author":"S. Narayanan","year":"1993","unstructured":"S. Narayanan, R. Gupta, and M.A. Breuer, ?Optimal Configuring of Multiple Scan Chains,?IEEE Transactions on Computers, Vol. 42, No. 9, pp. 1121?1131, September 1993.","journal-title":"IEEE Transactions on Computers"},{"key":"CR31","doi-asserted-by":"crossref","unstructured":"S. Bhawmik, M.S. Khaira, P.P. Mishra, A. Das, and A. Dasgupta, ?Threading of Multiple Scan Paths in a VLSI Circuit,?Proc. International Test Conference, pp. 735?743, September 1988.","DOI":"10.1109\/TEST.1988.207859"},{"key":"CR32","doi-asserted-by":"crossref","unstructured":"R.G. Bennetts and F.P.M. Beenker, ?Partial Scan: What Problem Does It Solve??Proc. European Test Conference, pp. 99?106, April 1993.","DOI":"10.1109\/ETC.1993.246528"},{"key":"CR33","doi-asserted-by":"crossref","unstructured":"J. Steensma, F. Catthoor, and H. De Man, ?Adding Hardware for Testability in Synthesized Data Paths,?Proc. European Conferece on Design Automation, pp. 156?160, February 1993.","DOI":"10.1109\/EDAC.1993.386483"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF00993311.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/BF00993311\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF00993311","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,22]],"date-time":"2024-12-22T16:15:57Z","timestamp":1734884157000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/BF00993311"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,8]]},"references-count":33,"journal-issue":{"issue":"1-2","published-print":{"date-parts":[[1995,8]]}},"alternative-id":["BF00993311"],"URL":"https:\/\/doi.org\/10.1007\/bf00993311","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[1995,8]]}}}