{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:25:33Z","timestamp":1749205533011},"reference-count":21,"publisher":"Springer Science and Business Media LLC","issue":"1-2","license":[{"start":{"date-parts":[[1995,1,1]],"date-time":"1995-01-01T00:00:00Z","timestamp":788918400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[1995]]},"DOI":"10.1007\/bf00993312","type":"journal-article","created":{"date-parts":[[2005,1,14]],"date-time":"2005-01-14T18:06:31Z","timestamp":1105725991000},"page":"25-46","source":"Crossref","is-referenced-by-count":18,"title":["Partial scan design of register-transfer level circuits"],"prefix":"10.1007","volume":"7","author":[{"given":"Rajesh","family":"Gupta","sequence":"first","affiliation":[]},{"given":"Melvin A.","family":"Breuer","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"CR1","unstructured":"E.B. Eichelberger and T.W. Williams, ?A logic design structure for LSI testability,?Proceedings 14th Design Automation Conference, pp. 462?467, June 1977."},{"key":"CR2","doi-asserted-by":"crossref","first-page":"46","DOI":"10.1109\/T-C.1973.223600","volume":"22","author":"M.J.Y. Williams","year":"1973","unstructured":"M.J.Y. Williams and J.B. Angell, ?Enhancing testability of LSI circuits via test points and additional logic,?IEEE Transactions on Computers, Vol. C-22, pp. 46?60, 1973.","journal-title":"IEEE Transactions on Computers"},{"key":"CR3","unstructured":"J.H. Stewart, ?Future testing of large LSI circuit cards,?Digest of Papers, IEEE Semiconductor Test Conference, pp. 6?15, October 1977."},{"key":"CR4","unstructured":"S. Funatsu, N. Wakatsuki, and A. Yamada, ?Designing digital circuits with easily testable consideration,?Digest of Papers, IEEE Semiconductor Test Conference, pp. 98?102, 1978."},{"key":"CR5","volume-title":"Digital Systems Testing and Testable Design","author":"M. Abramovici","year":"1990","unstructured":"M. Abramovici, M.A. Breuer, and A.D. Friedman,Digital Systems Testing and Testable Design. W.H. Freeman & Co., New York, 1990."},{"issue":"No. 2","key":"CR6","first-page":"56","volume":"13","author":"E. Trischler","year":"1984","unstructured":"E. Trischler, ?Design for testability using incomplete scan path and testability analysis,?Siemens Forsch.-u. Entwickl.-Ber., Vol. 13, No. 2, pp. 56?61, 1984.","journal-title":"Siemens Forsch.-u. Entwickl.-Ber."},{"key":"CR7","doi-asserted-by":"crossref","unstructured":"H.-K.T. Ma, S. Devadas, A.R. Newton, and A. Sangiovanni-Vincentelli, ?An incomplete scan design approach to test generation for sequential machines,?Proceedings IEEE International Test Conference, pp. 730?734, September 1988.","DOI":"10.1109\/TEST.1988.207858"},{"key":"CR8","doi-asserted-by":"crossref","unstructured":"K.-T. Cheng and V.D. Agrawal, ?An economical scan design for sequential logic test generation,?Proceedings Fault-Tolerant Computing Symposium (FTCS-19), pp. 28?35, June 1989.","DOI":"10.1109\/FTCS.1989.105539"},{"key":"CR9","doi-asserted-by":"crossref","unstructured":"R. Gupta, R. Gupta, and M.A. Breuer, ?BALLAST: A methodology for partial scan design,? InProceedings Fault-Tolerant Computing Symposium (FTCS-19), pp. 118?125, June 1989.","DOI":"10.1109\/FTCS.1989.105553"},{"key":"CR10","doi-asserted-by":"crossref","unstructured":"A. Kunzmann. ?Produktionstest synchroner Schaltwerke auf der Basis von Pipelinestrukturen,?Proceedings 18 Jahrestagung der Gesellschaft f\u00fcr Informatik, Hamburg, Informatik-Fachberichte 188, Springer-Verlag, pp. 92?105, 1988.","DOI":"10.1007\/978-3-642-74135-7_6"},{"key":"CR11","doi-asserted-by":"crossref","unstructured":"V. Chickermane and J.H. Patel, ?An optimization based approach to the partial scan design problem,?Proceedings IEEE International Test Conference, pp. 377?386, September 1990.","DOI":"10.1109\/TEST.1990.114045"},{"key":"CR12","unstructured":"R. Woudsma, F.P.M. Beenker, J.L. van Meerbergen, and C. Niessen, ?PIRAMID: An architecture-driven silicon compiler for complex DSP applications,?Proceeding International Symposium on Circuits and Systems, pp. 2596?2600, May 1990."},{"issue":"No. 4","key":"CR13","doi-asserted-by":"crossref","first-page":"538","DOI":"10.1109\/12.54846","volume":"39","author":"R. Gupta","year":"1990","unstructured":"R. Gupta, R. Gupta, and M.A. Breuer, ?The BALLAST methodology for structured partial scan design,?IEEE Transactions on Computers, Vol. 39, No. 4, pp. 538?543, April 1990.","journal-title":"IEEE Transactions on Computers"},{"key":"CR14","unstructured":"R. Gupta,Advanced Serial Scan Design for Testability, Ph.D. thesis, University of Southern California, Department of Electrical Engineering-Systems, 1991."},{"key":"CR15","doi-asserted-by":"crossref","unstructured":"D.H. Lee and S.M. Reddy, ?On determining scan flip-flops in partial scan designs,?Proceedings IEEE International Conference on Computer-Aided Design, pp. 322?325, November 1990.","DOI":"10.1109\/ICCAD.1990.129914"},{"key":"CR16","doi-asserted-by":"crossref","unstructured":"S. Narayananan, C.A. Njinda, R. Gupta, and M.A. Breuer, ?A multi-facet scan design system,?Proceedings, European Design Automation Conference, pp. 246?251, September 1992.","DOI":"10.1109\/EURDAC.1992.246236"},{"issue":"No. 4","key":"CR17","doi-asserted-by":"crossref","first-page":"56","DOI":"10.1109\/MDT.1985.294746","volume":"2","author":"M.S. Abadir","year":"1985","unstructured":"M.S. Abadir and M.A. Breuer, ?A knowledge-based system for designing testable VLSI chips,?IEEE Design & Test of Computers, Vol. 2, No. 4, pp. 56?68, August 1985.","journal-title":"IEEE Design & Test of Computers"},{"key":"CR18","doi-asserted-by":"crossref","unstructured":"R. Gupta and M.A. Breuer, ?Ordering storage elements in a single scan chain,?Proceedings International Conference on Computer-Aided Design, pp. 408?411, November 1991.","DOI":"10.1109\/ICCAD.1991.185289"},{"issue":"No. 9","key":"CR19","doi-asserted-by":"crossref","first-page":"1121","DOI":"10.1109\/12.241600","volume":"42","author":"S. Narayanan","year":"1993","unstructured":"S. Narayanan, R. Gupta, and M.A. Breuer, ?Optimal configuring of multiple scan chains,?IEEE Transactions on Computers, Vol. 42, No. 9, pp. 1121?1131, September 1993.","journal-title":"IEEE Transactions on Computers"},{"key":"CR20","unstructured":"D. Ha,Automatic Test Pattern Generators and Fault Simulators for Combinational and Sequential Circuits, Technical Report, Virginia Polytechnic Institute, June 1992."},{"issue":"No. 11","key":"CR21","doi-asserted-by":"crossref","first-page":"1361","DOI":"10.1109\/12.247839","volume":"42","author":"T.P. Kelsey","year":"1993","unstructured":"T.P. Kelsey, K.K. Saluja, and S.Y. Lee, ?An efficient algorithm for sequential circuit test generation,?IEEE Transactions on Computers, Vol. 42, No. 11, pp. 1361?1371, November 1993.","journal-title":"IEEE Transactions on Computers"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF00993312.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/BF00993312\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF00993312","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,5,1]],"date-time":"2023-05-01T16:07:39Z","timestamp":1682957259000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/BF00993312"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995]]},"references-count":21,"journal-issue":{"issue":"1-2","published-print":{"date-parts":[[1995]]}},"alternative-id":["BF00993312"],"URL":"https:\/\/doi.org\/10.1007\/bf00993312","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"value":"0923-8174","type":"print"},{"value":"1573-0727","type":"electronic"}],"subject":[],"published":{"date-parts":[[1995]]}}}