{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:25:31Z","timestamp":1749205531379,"version":"3.32.0"},"reference-count":30,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[1995,12,1]],"date-time":"1995-12-01T00:00:00Z","timestamp":817776000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[1995,12]]},"DOI":"10.1007\/bf00995311","type":"journal-article","created":{"date-parts":[[2005,1,18]],"date-time":"2005-01-18T17:52:57Z","timestamp":1106070777000},"page":"157-172","source":"Crossref","is-referenced-by-count":2,"title":["Efficient multiple path propagating tests for delay faults"],"prefix":"10.1007","volume":"7","author":[{"given":"Ankan K.","family":"Pramanick","sequence":"first","affiliation":[]},{"given":"Sudhakar M.","family":"Reddy","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"CR1","unstructured":"E.P. Hsieh et al., ?Delay Test Generation?Proc. 14th ACM\/IEEE Design Automation Conf., June 1977, pp. 486?491."},{"key":"CR2","doi-asserted-by":"crossref","first-page":"235","DOI":"10.1109\/TC.1980.1675555","volume":"29","author":"J.P. Lesser","year":"1980","unstructured":"J.P. Lesser and J.J. Shedletsky, ?An Experimental Delay Test Generator for LSI Logic,?IEEE Transactions on Computers, Vol. C-29, pp. 235?248, March 1980.","journal-title":"IEEE Transactions on Computers"},{"key":"CR3","unstructured":"Y.K. Malaiya and R. Narayanswamy, ?Testing for Timing Faults in Synchronous Sequential Integrated Circuits,?Proc. IEEE International Test Conf., October 1983, pp. 560?571."},{"key":"CR4","unstructured":"T. Hayashi et al., ?A Delay Test Generator for Logic LSI,?Proc. 14th IEEE International Fault Tolerant Computing Symp., June 1984, pp. 146?149."},{"key":"CR5","unstructured":"K.D. Wagner, ?The Error Latency of Delay Faults in Combinational and Sequential Circuits,?Proc. IEEE International Test Conf., November 1985, pp. 334?341."},{"key":"CR6","unstructured":"G.L. Smith, ?Model for Delay Faults Based Upon Paths,?Proc. IEEE International Test Conf., November 1985, pp. 342?349."},{"key":"CR7","unstructured":"J. Savir and W.H. McAnney, ?Random Pattern Testability of Delay Faults,?Proc. IEEE International Test Conf., September 1986, pp. 263?273."},{"key":"CR8","unstructured":"K.D. Wagner, ?Delay Testing of Digital Circuits Using Pseudorandom Input Sequences,?Center for Reliable Computing Report 85-12, Stanford University, revised March 1986."},{"key":"CR9","doi-asserted-by":"crossref","first-page":"694","DOI":"10.1109\/TCAD.1987.1270315","volume":"6","author":"C.J. Lin","year":"1987","unstructured":"C.J. Lin and S.M. Reddy, ?On Delay Fault Testing in Logic Circuits,?IEEE Transactions on CAD\/ICAS, Vol. CAD-6, pp. 694?703, September 1987.","journal-title":"IEEE Transactions on CAD\/ICAS"},{"key":"CR10","unstructured":"S.M. Reddy et al., ?An Automatic Test Pattern Generator for the Detection of Path Delay Faults,?Proc. IEEE International Conf. on CAD, November 1987, pp. 284?287."},{"key":"CR11","unstructured":"E.S. Park and M.R. Mercer, ?Robust and Nonrobust Tests for Path Delay Faults in a Combinational Circuit,?Proc. IEEE International Test Conf., September 1987, pp. 1027?1034."},{"key":"CR12","doi-asserted-by":"crossref","unstructured":"M.H. Schulz et al., ?Advanced Automatic Test Pattern Generation Techniques for Path Delay Faults,?Proc. 19th IEEE International Fault Tolerant Computing Symp., June 1989. pp. 44?51.","DOI":"10.1109\/FTCS.1989.105541"},{"key":"CR13","doi-asserted-by":"crossref","first-page":"1036","DOI":"10.1109\/43.85740","volume":"10","author":"S. Kundu","year":"1991","unstructured":"S. Kundu et al., ?On the Design of Robustly Testable CMOS Combinational Logic Circuits,?IEEE Transactions on CAD\/ICAS, Vol. CAD-10, pp. 1036?1048, August 1991.","journal-title":"IEEE Transactions on CAD\/ICAS"},{"key":"CR14","doi-asserted-by":"crossref","unstructured":"K. Roy et al., ?Synthesis of Delay Fault Testable Combinational Logic,?Proc. IEEE International Conference on CAD, November 1989, pp. 418?421.","DOI":"10.1109\/ICCAD.1989.76982"},{"key":"CR15","doi-asserted-by":"crossref","unstructured":"A.K. Pramanick et al., ?Synthesis of Combinational Logic Circuits for Path Delay Fault Testability,?Proc. IEEE International Symp. on Circuits and Systems, May 1990, pp. 3105?3108.","DOI":"10.1109\/ISCAS.1990.112669"},{"key":"CR16","doi-asserted-by":"crossref","unstructured":"A.K. Pramanick and S.M. Reddy, ?On the Design of Path Delay Fault Testable Combinational Circuits,?Proc. IEEE International Fault Tolerant Computing Symp., June 1990, pp. 374?381.","DOI":"10.1109\/FTCS.1990.89391"},{"key":"CR17","unstructured":"S. Devadas and K. Keutzer, ?Necessary and Sufficient Conditions for Robust Path Delay Fault Testability,?Advanced Research in VLSI, Proc. of the 8th MIT Conference, MIT Press, April 1990."},{"key":"CR18","unstructured":"J.L. Carter et al., ?Efficient Test Coverage Determination for Delay Faults,?Proc. IEEE International Test Conf., September 1987, pp. 418?427."},{"key":"CR19","doi-asserted-by":"crossref","unstructured":"A.K. Pramanick and S.M. Reddy, ?On the Detection of Delay Faults,?Proc. IEEE International Test Conf., September 1988, pp. 845?856.","DOI":"10.1109\/TEST.1988.207872"},{"key":"CR20","doi-asserted-by":"crossref","unstructured":"V.S. Iyengar et al., ?Delay Test Generation 1?Concepts and Coverage Metrics,?Proc. IEEE International Test Conf., September 1988, pp. 857?866.","DOI":"10.1109\/TEST.1988.207873"},{"key":"CR21","doi-asserted-by":"crossref","first-page":"299","DOI":"10.1109\/43.46805","volume":"9","author":"V.S. Iyengar","year":"1990","unstructured":"V.S. Iyengar et al., ?On Computing the Sizes of Detected Delay Faults,IEEE Transactions on CAD\/ICAS, Vol. CAD-9, pp. 299?312, March 1990.","journal-title":"IEEE Transactions on CAD\/ICAS"},{"key":"CR22","doi-asserted-by":"crossref","unstructured":"A.K. Pramanick and S.M. Reddy, ?On the Computation of the Ranges of Detected Delay Fault Sizes,?Proc. IEEE International Conf. on CAD, November 1989, pp. 126?129.","DOI":"10.1109\/ICCAD.1989.76919"},{"key":"CR23","doi-asserted-by":"crossref","unstructured":"A.K. Pramanick and S.M. Reddy, ?On the Fault Coverage of Delay Fault Detecting Tests,?Proc. IEEE European Design Automation Conf., March 1990, pp. 334?338.","DOI":"10.1109\/EDAC.1990.136669"},{"key":"CR24","doi-asserted-by":"crossref","unstructured":"B.P. Serlet, ?Fast, Small and Static Combinational CMOS Circuits,?Proc. 24th ACM\/IEEE Design Automation Conf., June 1987, pp. 451?457.","DOI":"10.1145\/37888.37955"},{"key":"CR25","doi-asserted-by":"crossref","unstructured":"G. Hachtel et al., ?On the Properties of Algebraic Transformations and the Multifault Testability of Multilevel Logic,?Proc. IEEE International Conf. on CAD, November 1989, pp. 422?425.","DOI":"10.1109\/ICCAD.1989.76983"},{"key":"CR26","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4613-2821-6","volume-title":"Logic Minimization Algorithms for VLSI Synthesis","author":"R.K. Brayton","year":"1984","unstructured":"R.K. Brayton et al.Logic Minimization Algorithms for VLSI Synthesis, Boston, Kluwer Academic Publishers, 1984."},{"key":"CR27","doi-asserted-by":"crossref","first-page":"1062","DOI":"10.1109\/TCAD.1987.1270347","volume":"6","author":"R.K. Brayton","year":"1987","unstructured":"R.K. Brayton et al., ?MIS: A Multiple-Level Logic Optimization System,?IEEE Transactions on CAD\/ICAS, Vol. CAD-6, pp. 1062?1081, November 1987.","journal-title":"IEEE Transactions on CAD\/ICAS"},{"key":"CR28","unstructured":"E.J. McCluskey, ?Transients in Combinational Logic Circuits,?Redundancy Techniques for Computing Systems (Wilcox and Mann, eds.), Spartan Books, 1962."},{"key":"CR29","doi-asserted-by":"crossref","first-page":"31","DOI":"10.1109\/T-C.1972.223428","volume":"21","author":"J.W. Gault","year":"1972","unstructured":"J.W. Gault et al., ?Multiple Fault Detection in Combinational Networks,?IEEE Transactions on Computers, Vol. C-21, pp. 31?36, January 1972.","journal-title":"IEEE Transactions on Computers"},{"key":"CR30","doi-asserted-by":"crossref","first-page":"87","DOI":"10.1109\/43.108622","volume":"11","author":"S. Devadas","year":"1992","unstructured":"S. Devadas et al., ?Synthesis of Robust Delay Fault Testable Circuits: Theory,?IEEE Transactions on CAD\/ICAS, Vol. CAD-11, pp. 87?101, January 1992.","journal-title":"IEEE Transactions on CAD\/ICAS"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF00995311.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/BF00995311\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF00995311","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,22]],"date-time":"2024-12-22T17:08:45Z","timestamp":1734887325000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/BF00995311"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,12]]},"references-count":30,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1995,12]]}},"alternative-id":["BF00995311"],"URL":"https:\/\/doi.org\/10.1007\/bf00995311","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[1995,12]]}}}