{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:58:15Z","timestamp":1759147095582,"version":"3.32.0"},"reference-count":33,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[1995,12,1]],"date-time":"1995-12-01T00:00:00Z","timestamp":817776000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[1995,12]]},"DOI":"10.1007\/bf00995312","type":"journal-article","created":{"date-parts":[[2005,1,18]],"date-time":"2005-01-18T17:52:57Z","timestamp":1106070777000},"page":"173-191","source":"Crossref","is-referenced-by-count":11,"title":["On local transformations and path delay fault testability"],"prefix":"10.1007","volume":"7","author":[{"given":"Harry","family":"Hengster","sequence":"first","affiliation":[]},{"given":"Rolf","family":"Drechsler","sequence":"additional","affiliation":[]},{"given":"Bernd","family":"Becker","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"CR1","volume-title":"Digital Systems Testing and Testable Design","author":"M. Abramovici","year":"1990","unstructured":"M. Abramovici, M.A. Breuer, and A.D. Friedman,Digital Systems Testing and Testable Design, Computer Science Press, New York, 1990."},{"key":"CR2","doi-asserted-by":"crossref","unstructured":"R.L. Wadsack, ?Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits,?Bell System Technical Jour., 57, 1978.","DOI":"10.1002\/j.1538-7305.1978.tb02106.x"},{"key":"CR3","unstructured":"G.L. Smith, ?Model for Delay Faults Based Upon Paths,?Proc. of Int'l Test Conf., 1985, pp. 342?349."},{"key":"CR4","unstructured":"E. Lindbloom, J.A. Waicukauski, B. Rosen, and V. Iyengar, ?Transition Fault Simulation by Parallel Pattern Single Fault Propagation,?Proc. of Int'l Test Conf., 1986, pp. 542?549."},{"key":"CR5","unstructured":"S.M. Reddy, C.J. Lin, and S. Patil, ?An Automatic Test Pattern Generator for the Detection of Path Delay Faults,?Proc. of Int'l Conf. on CAD, 1987, pp. 284?287."},{"issue":"10","key":"CR6","doi-asserted-by":"crossref","first-page":"1323","DOI":"10.1109\/43.88928","volume":"10","author":"K. Fuchs","year":"1991","unstructured":"K. Fuchs, F. Fink and M.H. Schulz, ?DYNAMITE: An Efficient Automatic Test Pattern Generation System for Path Delay Faults,IEEE Trans. on CAD, Vol 10(10), pp. 1323?1335, 1991.","journal-title":"IEEE Trans. on CAD"},{"key":"CR7","doi-asserted-by":"crossref","unstructured":"S. Devadas and K. Keutzer, ?Necessary and Sufficient Conditions for Robust Delay-Fault Testability of Logic Circuits,?Sixth MIT Conference on Advanced Research on VLSI, 1990, pp. 221?238.","DOI":"10.1145\/123186.123262"},{"key":"CR8","doi-asserted-by":"crossref","unstructured":"A.K. Pramanick and S.M. Reddy, ?On the Design of Path Delay Fault Testable Combinational Circuits,?Proc. of Int'l Symp on Fault-Tolerant Comp., 1990, pp. 374?381.","DOI":"10.1109\/FTCS.1990.89391"},{"key":"CR9","unstructured":"K. Fuchs, M. Pabst, and T. R\u00f6ssel, ?Improved Redundancy Identification and Factorization for the Synthesis of Robustly Path Delay Fault Testable Circuits,?Proc. of IFIP Workshop on Logic and Architecture Synthesis, 1993, pp. 413?432."},{"key":"CR10","doi-asserted-by":"crossref","unstructured":"N.K. Jha, I. Pomeranz, S.M. Reddy, and R.J. Miller, ?Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability,?Proc. of Int'l Symp. on Fault-Tolerant Comp., 1992, pp. 280?287.","DOI":"10.1109\/FTCS.1992.243573"},{"key":"CR11","doi-asserted-by":"crossref","unstructured":"K. Roy, J.A. Abraham, K. De, and S. Lusky, ?Synthesis of Delay Fault Testable Combinational Logic,?Proc. of Int'l Conf. on CAD, 1989, pp. 418?421.","DOI":"10.1109\/ICCAD.1989.76982"},{"key":"CR12","doi-asserted-by":"crossref","unstructured":"S. Kundu and A.K. Pramanick, ?Testability Preserving Boolean Transforms for Logic Synthesis,?Proc. of VLSI Test Symp., 1993, pp. 131?138.","DOI":"10.1109\/VTEST.1993.313336"},{"key":"CR13","doi-asserted-by":"crossref","unstructured":"S. Devadas and K. Keutzer, ?Synthesis and Optimization Procedures for Robust Delay-Fault Testable Combinational Logic Circuits,?Proc. of Design Automation Conf., 1990, pp. 221?227.","DOI":"10.1145\/123186.123262"},{"key":"CR14","doi-asserted-by":"crossref","unstructured":"M.J. Bryan, S. Devadas, and K. Keutzer, ?Testability-Preserving Circuit Transformations,?Proc. of Int'l Conf. on CAD, 1990, pp. 456?459.","DOI":"10.1109\/ICCAD.1990.129952"},{"key":"CR15","doi-asserted-by":"crossref","unstructured":"J. Rajski and J. Vasudevamurthy, ?Testability Preserving Transformations in Multi-Level Logic Synthesis,?Proc. of Int'l Test Conf., 1990, pp. 265?273.","DOI":"10.1109\/TEST.1990.114032"},{"key":"CR16","unstructured":"S. Chakravarty, ?A Study of Theoretical Issues in the Synthesis of Delay Fault Testable Circuits,?Int'l Workshop on Logic Synth., 1993, pp. P4 d:1?10."},{"issue":"8","key":"CR17","doi-asserted-by":"crossref","first-page":"677","DOI":"10.1109\/TC.1986.1676819","volume":"35","author":"R.E. Bryant","year":"1986","unstructured":"R.E. Bryant, ?Graph-Based Algorithms for Boolean Function Manipulation,?IEEE Trans. on Comp., Vol. 35(8), pp. 677?691, 1986.","journal-title":"IEEE Trans. on Comp."},{"issue":"2","key":"CR18","doi-asserted-by":"crossref","first-page":"461","DOI":"10.1145\/42282.46161","volume":"35","author":"I. Wegner","year":"1988","unstructured":"I. Wegner, ?On the Complexity of Branching Programs and Decision Trees for Clique Functions,?Jour. of the ACM, Vol. 35(2), pp. 461?471, 1988.","journal-title":"Jour. of the ACM"},{"key":"CR19","doi-asserted-by":"crossref","unstructured":"M. Ajtai, L. Babai, P. Hajnal, J. Komlos, P. Pudlak, V. R\u00f6dl, E. Szemeredi, and G. Turan, ?Two Lower Bounds for Branching Programs,?Proc. of Symp. on the Theory of Computing, 1986, pp. 30?38.","DOI":"10.1145\/12130.12134"},{"issue":"2","key":"CR20","doi-asserted-by":"crossref","first-page":"205","DOI":"10.1109\/12.73590","volume":"40","author":"R.E. Bryant","year":"1991","unstructured":"R.E. Bryant, ?On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication,?IEEE Trans. on Comp., Vol. 40(2), pp. 205?213, 1991.","journal-title":"IEEE Trans. on Comp."},{"issue":"1","key":"CR21","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1016\/0167-9260(93)90002-T","volume":"15","author":"P. Ashar","year":"1993","unstructured":"P. Ashar, S. Devadas, and K. Keutzer, ?Path-Delay-Fault Testability Properties of Multiplexor-Based Networks,?Integration the VLSI Jour., Vol. 15(1), pp. 1?23, 1993.","journal-title":"Integration the VLSI Jour."},{"key":"CR22","unstructured":"R. Drechsler and B. Becker, ?Rapid Prototyping of Robust Path-Delay-Fault Testable Circuits Derived from Binary Decision Diagrams,? Technical Report, University of Saarland, 1992, TR-17\/92, SFB 124."},{"key":"CR23","doi-asserted-by":"crossref","unstructured":"S. Kundu and S.M. Reddy, ?On the Design of Robust Testable CMOS Combinational Logic Circuits,?Proc. of Int'l Symp. on Fault-Tolerant Comp., 1988, pp. 220?225.","DOI":"10.1109\/FTCS.1988.5323"},{"key":"CR24","unstructured":"B. Kapoor and V. Nair, ?Heuristics for Shannon Decomposition in Area-Efficient Realization of Fully Robust Path Delay Fault Testable Digital Logic,?Int'l Workshop on Logic Symth., 1993, pp. P4c: 1?8."},{"key":"CR25","doi-asserted-by":"crossref","unstructured":"A.K. Pramanick, S.M. Reddy, and S. Sengupta, ?Synthesis of Combinational Logic Circuits for Path Delay Fault Testability,?Proc. of Int's Symp. Circ. and Systems, 1990, pp. 3105?3108.","DOI":"10.1109\/ISCAS.1990.112669"},{"issue":"1","key":"CR26","doi-asserted-by":"crossref","first-page":"66","DOI":"10.1109\/PGEC.1966.264376","volume":"15","author":"D.B. Armstrong","year":"1966","unstructured":"D.B. Armstrong, ?On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic Nets,?IEEE Trans. on Electronic Comp., Vol. 15(1), pp. 66?73, 1966.","journal-title":"IEEE Trans. on Electronic Comp."},{"key":"CR27","doi-asserted-by":"crossref","unstructured":"B. Becker, Th. Burch, G. Hotz, D. Kiel, R. Kolla, P. Molitor, H.G. Osthof, G. Pitsch, and U. Sparmann, ?A Graphical System for Hierarchical Specifications and Checkups of VLSI Circuits,?Proc. of European Conf. on Design Automation, 1990, pp. 174?179.","DOI":"10.1109\/EDAC.1990.136640"},{"key":"CR28","doi-asserted-by":"crossref","unstructured":"R.K. Brayton, G.D. Hachtel, C. McMullen, and A.L. Sangiovanni-Vincentelli,Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, 1984.","DOI":"10.1007\/978-1-4613-2821-6"},{"key":"CR29","unstructured":"F. Brglez and H. Fujiwara, ?A Neutral Netlist of 10 Combinational Circuits and a Target Translator in Fortran,?Proc. of Int'l Symp. Circ. and Systems, Special Sess. on ATPG and Fault Simulation, 1985, pp. 663?698."},{"key":"CR30","doi-asserted-by":"crossref","unstructured":"F. Brglez, D. Bryan, and K. Kozminski, ?Combinational Profiles of Sequential Benchmark Circuits,?Proc. of Int'l Symp. Circ. and Systems, 1989, pp. 1929?1934.","DOI":"10.1109\/ISCAS.1989.100747"},{"key":"CR31","unstructured":"R. Drechsler, ?BiTeS: A BDD Based Test Pattern Generator for Strong Robust Path Delay Faults,?Proc. of European Design Automation Conf., 1994, pp. 322?327."},{"key":"CR32","doi-asserted-by":"crossref","unstructured":"H. Hengster, R. Drechsler, and B. Becker, ?Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model,?Proc. of 7th International Conf. on VLSI Design Conf., 1994, pp. 123?126.","DOI":"10.1109\/ICVD.1994.282669"},{"key":"CR33","doi-asserted-by":"crossref","unstructured":"H. Hengster, R. Drechsler, and B. Becker, ?On the Application of Local Circuit Transformation with Special Emphasis on Path Delay Fault Testability,?Proc. of VLSI Test Symp., 1995, pp. 387?392.","DOI":"10.1109\/VTEST.1995.512665"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF00995312.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/BF00995312\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF00995312","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,22]],"date-time":"2024-12-22T17:08:45Z","timestamp":1734887325000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/BF00995312"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,12]]},"references-count":33,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1995,12]]}},"alternative-id":["BF00995312"],"URL":"https:\/\/doi.org\/10.1007\/bf00995312","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[1995,12]]}}}