{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T00:25:55Z","timestamp":1761611155079},"reference-count":8,"publisher":"Springer Science and Business Media LLC","issue":"1-2","license":[{"start":{"date-parts":[[1995,8,1]],"date-time":"1995-08-01T00:00:00Z","timestamp":807235200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Form Method Syst Des"],"published-print":{"date-parts":[[1995,8]]},"DOI":"10.1007\/bf01383871","type":"journal-article","created":{"date-parts":[[2005,4,2]],"date-time":"2005-04-02T02:10:10Z","timestamp":1112407810000},"page":"7-25","source":"Crossref","is-referenced-by-count":6,"title":["A formalization of a subset of VHDL in the Boyer-Moore logic"],"prefix":"10.1007","volume":"7","author":[{"given":"David M.","family":"Russinoff","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"CR1","volume-title":"A Computational Logic Handbook","author":"R.S. Boyer","year":"1988","unstructured":"R.S. Boyer and J. Moore,A Computational Logic Handbook. Academic Press, Boston, 1988."},{"key":"CR2","unstructured":"W. Damm, A Formal Semantics for VHDL Based on Interpreted Petri Nets. Technical Report, University of Oldenburg, 1992."},{"key":"CR3","unstructured":"Institute of Electrical and Electronic Engineers,Draft Standard VHDL Language Reference Manual, 1993."},{"key":"CR4","unstructured":"M. Kaufmann, A Translator from an HDL of David Russinoff to VHDL. Internal Note 278, Computational Logic, Inc., July 1993."},{"key":"CR5","unstructured":"D. Russinoff, Specification and Verification of Gate-Level VHDL Models of Synchronous and Asynchronous Circuits, to appear inSpecification and Validation Methods, edited by Egon B\u00f6rger, Oxford University Press, 1995; also available as Technical Report 99, Computational Logic, Inc., May 1994."},{"key":"CR6","unstructured":"L. Sanchez and C.D. Kloos, ?Functional Description of VHDL.? InSegundo Congreso de Programacion Declarativa PRODE 93, Spain, September 1993."},{"key":"CR7","volume-title":"Digital Integrated Electronics","author":"H. Taub","year":"1977","unstructured":"H. Taub and D. SchillingDigital Integrated Electronics. McGraw-Hill, New York, 1977."},{"key":"CR8","unstructured":"J. Van Tassel, A Formalization of the VHDL Simulation Cycle. Technical Report 249, University of Cambridge Computer Laboratory, June 1992."}],"container-title":["Formal Methods in System Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF01383871.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/BF01383871\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF01383871","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,2]],"date-time":"2019-05-02T16:04:45Z","timestamp":1556813085000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/BF01383871"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,8]]},"references-count":8,"journal-issue":{"issue":"1-2","published-print":{"date-parts":[[1995,8]]}},"alternative-id":["BF01383871"],"URL":"https:\/\/doi.org\/10.1007\/bf01383871","relation":{},"ISSN":["0925-9856","1572-8102"],"issn-type":[{"value":"0925-9856","type":"print"},{"value":"1572-8102","type":"electronic"}],"subject":[],"published":{"date-parts":[[1995,8]]}}}