{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T11:17:28Z","timestamp":1648984648032},"reference-count":14,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[1993,6,1]],"date-time":"1993-06-01T00:00:00Z","timestamp":738892800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J VLSI Sign Process Syst Sign Image Video Technol"],"published-print":{"date-parts":[[1993,6]]},"DOI":"10.1007\/bf01581958","type":"journal-article","created":{"date-parts":[[2005,4,28]],"date-time":"2005-04-28T08:14:32Z","timestamp":1114676072000},"page":"45-56","source":"Crossref","is-referenced-by-count":3,"title":["A general-purpose signal processor architecture for neurocomputing and preprocessing applications"],"prefix":"10.1007","volume":"6","author":[{"given":"Ulrich","family":"Ramacher","sequence":"first","affiliation":[]},{"given":"J\u00f6rg","family":"Beichter","sequence":"additional","affiliation":[]},{"given":"Nico","family":"Br\u00fcls","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[1993,6,1]]},"reference":[{"key":"BF01581958_CR1","unstructured":"DARPA Neural Network Study, pp. 34 (figure 2.14\u201315), pp. 330 (figure 28.5), AFCEA."},{"key":"BF01581958_CR2","unstructured":"H.P. Graf, et al., \u201cRecent developments of electronic neural nets in USA and Canada,\u201d U. Ramacher, U. R\u00fcckert, and J. Nossek, eds., inProceedings of the 2nd International Conference on Microelectronics for Neural Networks, 1991, pp. 471\u2013490."},{"key":"BF01581958_CR3","unstructured":"Y. Hirai, \u201cHardware implementation of neural networks in Japan,\u201d pp. 435\u2013454, ibid."},{"key":"BF01581958_CR4","first-page":"180","volume":"33","author":"M. Griffin","year":"1991","unstructured":"M. Griffin, et al., \u201cAn 11-million transistor neural network execution engine,\u201dDigest of Technical Papers of the Int. Solid State Circuits Conf, vol. 33, 1991, pp. 180.","journal-title":"Digest of Technical Papers of the Int. Solid State Circuits Conf"},{"key":"BF01581958_CR5","doi-asserted-by":"crossref","unstructured":"M. Yasunaga, et al., Design, fabrication and evaluation of a 5-inch wafer scale neural network LSI composed of 576 digital neurons,\u201dProceedings of the IJCNN-90, vol. II, 1990, pp. 527\u2013535.","DOI":"10.1109\/IJCNN.1990.137618"},{"key":"BF01581958_CR6","unstructured":"L. Curran, \u201cWafer scale integration arrives in \u2018disk\u2019 form,\u201d inElectronic Design, Oct. 26, 1989, pp. 51\u201354."},{"key":"BF01581958_CR7","doi-asserted-by":"crossref","unstructured":"U. Ramacher, \u201cHardware concepts of neural networks,\u201d in R. Eckmiller,Advanced Neurocomputers, Elsevier, 1990, pp. 209\u2013218.","DOI":"10.1016\/B978-0-444-88400-8.50029-7"},{"key":"BF01581958_CR8","doi-asserted-by":"crossref","unstructured":"U. Ramacher, \u201cHamiltonian dynamics of neural networks,\u201dProceedings of the IJCNN-91, 1991.","DOI":"10.1007\/978-1-4615-3994-0"},{"key":"BF01581958_CR9","unstructured":"L.B. Almeida,IEEE Int. Conf. on Neural Networks, 1987, pp. II-609."},{"key":"BF01581958_CR10","doi-asserted-by":"crossref","first-page":"2229","DOI":"10.1103\/PhysRevLett.59.2229","volume":"59","author":"F.J. Pineda","year":"1987","unstructured":"F.J. Pineda,Phys. Rev. Letters, vol. 59, 1987, pp. 2229.","journal-title":"Phys. Rev. Letters"},{"key":"BF01581958_CR11","doi-asserted-by":"crossref","first-page":"263","DOI":"10.1162\/neco.1989.1.2.263","volume":"1","author":"B.A. Pearlmutter","year":"1989","unstructured":"B.A. Pearlmutter,Neural Computation, vol. 1, 1989, pp. 263.","journal-title":"Neural Computation"},{"key":"BF01581958_CR12","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-3994-0","volume-title":"VLSI Design of Neural Networks","author":"U. Ramacher","year":"1991","unstructured":"U. Ramacher et al., \u201cDesign of a 1st generation neurocomputer,\u201d in U. Ramacher, U. R\u00fcckert, eds.VLSI Design of Neural Networks, Boston: Kluwer Academic Publishers, 1991."},{"key":"BF01581958_CR13","doi-asserted-by":"crossref","unstructured":"U. Ramacher and M. Wesseling, \u201cWSI architecture of a neurocomputer module,\u201dProc. of the IEEE Int. Conf On Wafer Scale Integration, 1990, pp. 125\u2013130.","DOI":"10.1109\/ICWSI.1990.63892"},{"key":"BF01581958_CR14","doi-asserted-by":"crossref","unstructured":"U. Totzeck, F. Matthiesen, S. Wohlleben, and G. Noll, \u201cCMOS VLSI implementation of the 2D-DCT with linear processor arrays,\u201dProc. of IEEE ICASSP-90, pp. 937\u2013940.","DOI":"10.1109\/ICASSP.1990.116011"}],"container-title":["Journal of VLSI signal processing systems for signal, image and video technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF01581958.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/BF01581958\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF01581958","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,4,7]],"date-time":"2020-04-07T03:44:03Z","timestamp":1586231043000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/BF01581958"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1993,6]]},"references-count":14,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1993,6]]}},"alternative-id":["BF01581958"],"URL":"https:\/\/doi.org\/10.1007\/bf01581958","relation":{},"ISSN":["0922-5773"],"issn-type":[{"value":"0922-5773","type":"print"}],"subject":[],"published":{"date-parts":[[1993,6]]}}}