{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,31]],"date-time":"2025-12-31T00:08:38Z","timestamp":1767139718043,"version":"build-2238731810"},"reference-count":41,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[1993,8,1]],"date-time":"1993-08-01T00:00:00Z","timestamp":744163200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J VLSI Sign Process Syst Sign Image Video Technol"],"published-print":{"date-parts":[[1993,8]]},"DOI":"10.1007\/bf01607881","type":"journal-article","created":{"date-parts":[[2005,4,29]],"date-time":"2005-04-29T22:40:09Z","timestamp":1114814409000},"page":"191-214","source":"Crossref","is-referenced-by-count":5,"title":["High level synthesis and generating FPGAs with the BEDROC system"],"prefix":"10.1007","volume":"6","author":[{"given":"Miriam","family":"Leeser","sequence":"first","affiliation":[]},{"given":"Richard","family":"Chapman","sequence":"additional","affiliation":[]},{"given":"Mark","family":"Aagaard","sequence":"additional","affiliation":[]},{"given":"Mark","family":"Linderman","sequence":"additional","affiliation":[]},{"given":"Stephan","family":"Meier","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[1993,8,1]]},"reference":[{"key":"BF01607881_CR1","unstructured":"Paul Stanford and Paul Mancuso,Electronic Design Interchange Format Version 2 00, Electronic Industries Organization, second edition, 1989."},{"key":"BF01607881_CR2","unstructured":"High Level Synthesis Workshop, \u201cHigh level synthesis workshop benchmark set,\u201d 1991, Obtained by ftp from mcnc .org."},{"key":"BF01607881_CR3","doi-asserted-by":"crossref","first-page":"379","DOI":"10.1109\/TCAD.1986.1270207","volume":"CAD-5","author":"Chia-Jeng Tseng","year":"1986","unstructured":"Chia-Jeng Tseng and Daniel P. Siewiorek, \u201cAutomated synthesis of data paths in digital systems,\u201dIEEE Transaction on Computer-Aided Design, vol. CAD-5, pp. 379\u2013395, 1986.","journal-title":"IEEE Transaction on Computer-Aided Design"},{"key":"BF01607881_CR4","first-page":"257","volume-title":"VLSI and Modern Signal Processing","author":"P. Dewilde","year":"1985","unstructured":"P. Dewilde, E. Deprettere and R. Nouta, \u201cParallel and pipelined VLSI implementation of signal processing algorithms,\u201d S.Y. Kung, H.J. Whitehouse and T. Kailath, eds.,VLSI and Modern Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1985, Chap. 15, pp. 257\u2013275."},{"key":"BF01607881_CR5","volume-title":"Proceedings of 1992 European Design Automation Conference","author":"Houria Oudghiri","year":"1992","unstructured":"Houria Oudghiri and Bozena Kaminska, \u201cGlobal weighted scheduling and allocation algorithms,\u201dProceedings of 1992 European Design Automation Conference, IEEE Computer Society Press, Los Alamitas, CA, March 1992."},{"key":"BF01607881_CR6","doi-asserted-by":"crossref","first-page":"768","DOI":"10.1109\/43.31534","volume":"CAD-7","author":"Srinivas Devadas","year":"1989","unstructured":"Srinivas Devadas and Richard Newton, \u201cAlgorithms for hardware allocation in datapath synthesis,\u201dIEEE Transactions on CAD, CAD-7, pp. 768\u2013781, 1989.","journal-title":"IEEE Transactions on CAD"},{"key":"BF01607881_CR7","first-page":"14.7.1","volume-title":"Custom Integrated Circuits Conference","author":"L. Claesen","year":"1988","unstructured":"L. Claesen, F. Cathoor, D. Lanneer, G. Goossens, S. Note, J. Van Neerbergen and H. De Man, \u201cAutomatic synthesis of signal processing benchmark using the CATHEDRAL silicon compilers,\u201dCustom Integrated Circuits Conference, pp. 14.7.1\u201314.7.4 IEEE Press, New York, NY, 1988."},{"key":"BF01607881_CR8","volume-title":"Implementing Mathematics with the Nuprl Proof Development System","author":"R.L. Constable","year":"1986","unstructured":"R.L. Constableet al, Implementing Mathematics with the Nuprl Proof Development System, Englewood Cliffs, NJ: Prentice Hall, 1986."},{"key":"BF01607881_CR9","volume-title":"Formal Aspects of VLSI Design","author":"M.J.C. Gordon","year":"1986","unstructured":"M.J.C. Gordon, \u201cWhy higher-order logic is a good formalism for specifying and verifying hardware,\u201d G.J. Milne and P.A. Subrahmanyam, eds.,Formal Aspects of VLSI Design, Amsterdam: North-Holland, 1986."},{"key":"BF01607881_CR10","volume-title":"International Workshop on Formal Methods in VLSI Design","author":"Michael C. McFarland","year":"1991","unstructured":"Michael C. McFarland, \u201cA practical application of verification to high-level synthesis,\u201d P.A. Subramanyam, ed.,International Workshop on Formal Methods in VLSI Design, ACM, New York, NY, 1991."},{"key":"BF01607881_CR11","doi-asserted-by":"crossref","DOI":"10.1007\/0-387-97226-9","volume-title":"Proceedings of the MSI Workshop on Hardware Specification, Verification and Synthesis: Mathematical Aspects","author":"M.E. Leeser","year":"1990","unstructured":"M.E. Leeser and G.M. Brown,Proceedings of the MSI Workshop on Hardware Specification, Verification and Synthesis: Mathematical Aspects, Berlin\/New York: Springer Verlag, 1990."},{"key":"BF01607881_CR12","volume-title":"Proceedings of the 1992 European Design Automation Conference","author":"Richard Chapman","year":"1992","unstructured":"Richard Chapman, Geoffrey Brown, and Miriam Leeser, \u201cVerified high-level synthesis in BEDROC,\u201dProceedings of the 1992 European Design Automation Conference, IEEE Computer Society Press, Los Alamitas, CA, March 1992."},{"key":"BF01607881_CR13","doi-asserted-by":"crossref","unstructured":"Mark Aagaard and Miriam Leeser, \u201cVerifying a logic synthesis tool in Nuprl,\u201dWorkshop on Computer-Aided Verification, June 1992.","DOI":"10.1007\/3-540-56496-9_7"},{"key":"BF01607881_CR14","doi-asserted-by":"crossref","first-page":"301","DOI":"10.1109\/5.52214","volume":"78","author":"Michael C. McFarland","year":"1990","unstructured":"Michael C. McFarland, Alice C. Parker and Raul Camposano, \u201cThe high-level synthesis of digital systems,\u201dProceedings of the IEEE, vol. 78, pp. 301\u2013318, 1990.","journal-title":"Proceedings of the IEEE"},{"key":"BF01607881_CR15","doi-asserted-by":"crossref","first-page":"171","DOI":"10.1109\/43.21835","volume":"CAD-8","author":"R. Camposano","year":"1989","unstructured":"R. Camposano and W. Rosenstiel, \u201cSynthesizing circuits from behavioral descriptions,\u201dIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-8, pp. 171\u2013180, 1989.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"BF01607881_CR16","doi-asserted-by":"crossref","unstructured":"Giovanni De Micheli, David Ku, Frederic Mailhot and Thomas Truang, \u201cThe Olympus synthesis system,\u201dIEEE Design and Test of Computers, pp. 37\u201353, October 1990.","DOI":"10.1109\/54.60605"},{"key":"BF01607881_CR17","first-page":"337","volume-title":"25th Design Automation Conference","author":"D.E. Thomas","year":"1988","unstructured":"D.E. Thomas, E.M. Dirkes, R.A. Walker, J.V. Rajan, J.A. Nestor and R.L. Blackburn, \u201cThe system architect's workbench,\u201d25th Design Automation Conference, pp. 337\u2013343. IEEE Computer Society Press, Los Alamitas, CA, 1988."},{"key":"BF01607881_CR18","volume-title":"Silicon Compilation","author":"J. Rabaey","year":"1988","unstructured":"J. Rabaey, H. De Man, J. Vanhoof, G. Goossens and F. Catthoor, \u201cCathedral II: A synthesis system for multiprocessor DSP systems,\u201d Daniel D. Gajski, ed.,Silicon Compilation, Reading, MA: Addison-Wesley, 1988."},{"key":"BF01607881_CR19","doi-asserted-by":"crossref","unstructured":"Chee-Keng Chang, Geoffrey Brown and Miriam Leeser, \u201cEDISYN: A language-based editor for high-level synthesis,\u201dTenth International Symposium on Computer Hardware Description Languages, April 1991.","DOI":"10.1016\/B978-0-444-89208-9.50027-2"},{"key":"BF01607881_CR20","first-page":"271","volume-title":"FPGAs","author":"I. Page","year":"1991","unstructured":"I. Page and W. Luk, \u201cCompiling Occam into FPGAs,\u201d W. Moore and W. Luk, eds.,FPGAs, pp. 271\u2013283, Abingdon: EE & CS Books, 1991."},{"key":"BF01607881_CR21","doi-asserted-by":"crossref","unstructured":"Keshav Pingali, Micah Beck, Richard Johnson, Mayan Moudgill and Paul Stodghill, \u201cDependence Flow Graphs: An algebraic approach to program dependencies,\u201dProceedings of the 18th ACM Symposium on Principles of Programming Languages, 1991.","DOI":"10.1145\/99583.99595"},{"key":"BF01607881_CR22","unstructured":"M.C. McFarland, \u201cThe Value Tree: A database for automated digital design,\u201d Master's thesis, Carnegie-Mellon University, December 1978."},{"key":"BF01607881_CR23","doi-asserted-by":"crossref","unstructured":"Alex Orailoglu and Daniel Gajski, \u201cFlow graph representation,\u201dProceedings of 23rd Design Automation Conference, pp. 503\u2013509. IEEE, 1986.","DOI":"10.1109\/DAC.1986.1586135"},{"key":"BF01607881_CR24","unstructured":"Mark Genoe, Luc Claesen, Eric Verlind, Frank Proesmans, and Hugo De Man, \u201cAutomatic formal verification of Cathedral-II circuits from transistor switch level implementation up to high level behavioral specifications by thesfg tracing methodology,\u201dProceedings of the 1992 European Design Automation Conference, IEEE Press, March 1992."},{"key":"BF01607881_CR25","unstructured":"Luc Claesen, Frank Proesmans, Eric Verlind and Hugo De Man, \u201cSFG-Tracing: a methodology for the automatic verification of MOS transistor level implementations from high level behavioral specifications,\u201d P.A. Subrahmanyam, ed., 1992International Workshop on Formal Methods in VLSI Design, 1991."},{"key":"BF01607881_CR26","unstructured":"Jos T.V. Eijndhoven and Leon Stok, \u201cA data flow graph exchange format,\u201dProceedings of 1992 European Design Automation Conference, IEEE Press, March 1992."},{"key":"BF01607881_CR27","unstructured":"Miriam Leeser, Mark Aagaard, Mark Linderman, Richard Chapman, Richard Johnson and Stephan Meier, \u201cThe BEDROC high level synthesis system,\u201dASIC'91. IEEE, September 1991."},{"key":"BF01607881_CR28","doi-asserted-by":"crossref","unstructured":"P. Marwedel, \u201cA new synthesis algorithm for the MIMOLA software system,\u201d 23rd Design Automation Conference, pp. 271\u2013277. ACM\/IEEE, 1986.","DOI":"10.1109\/DAC.1986.1586100"},{"key":"BF01607881_CR29","doi-asserted-by":"crossref","unstructured":"M.C. McFarland, \u201cBUD: Bottom-up design of digital systems,\u201d 23rd Design Automation Conference, pp. 474\u2013479. ACM\/IEEE, 1986.","DOI":"10.1109\/DAC.1986.1586131"},{"key":"BF01607881_CR30","doi-asserted-by":"crossref","unstructured":"Alice C. Parker, Jorge Pizarro and Mitch Mlinar, \u201cMAHA: A program for datapath synthesis,\u201d23rd Design Automation Conference, pp. 461\u2013466. ACM\/IEEE, 1986.","DOI":"10.1145\/318013.318087"},{"key":"BF01607881_CR31","doi-asserted-by":"crossref","unstructured":"P.G. Paulin and J.P. Knight, \u201cForce-directed scheduling in automatic datapath synthesis,\u201d24th Design Automation Conference, pp. 195\u2013202. ACM\/IEEE, 1987.","DOI":"10.1145\/37888.37918"},{"key":"BF01607881_CR32","doi-asserted-by":"crossref","unstructured":"W.F.J. Verhaegh, E.H.L. Aarts, J.H.M. Korst and P.E.R. Lip-pens, \u201cImproved force-directed scheduling,\u201d InProceedings of the 1992 European Design Automation Conference, IEEE Press, March 1992.","DOI":"10.1109\/ICCAD.1992.279359"},{"key":"BF01607881_CR33","doi-asserted-by":"crossref","unstructured":"Pierre G. Paulin and John P. Knight, \u201cScheduling and binding algorithms for high-level synthesis,\u201d 26th Design Automation Conference, ACM\/IEEE, 1989.","DOI":"10.1145\/74382.74383"},{"key":"BF01607881_CR34","unstructured":"Richard E. Korf, \u201cReal-time heuristic search: First results,\u201dAAA1-87 Sixth National Conference on Artificial Intelligence, pp. 133\u2013138, 1987."},{"key":"BF01607881_CR35","unstructured":"Miriam Leeser and Stephan Meier, \u201cHardware scheduling with Real-Time A* search, \u201cProceedings of the Fifth International Workshop on High-Level Synthesis, 1991."},{"key":"BF01607881_CR36","unstructured":"R.K. Brayton and C. McMullen, \u201cDecomposition and factorization of Boolean expressions,\u201dInternational Symposium on Circuits and Systems, 1982."},{"key":"BF01607881_CR37","volume-title":"Designing Correct Circuits, Oxford 1990","author":"Mark Aagaard","year":"1991","unstructured":"Mark Aagaard and Miriam Leeser, \u201cThe implementation and proof of a Boolean simplification system,\u201d Geraint Jones and Mary Sheeran, eds.,Designing Correct Circuits, Oxford 1990, Berlin\/New York: Springer-Verlag, 1991."},{"key":"BF01607881_CR38","doi-asserted-by":"crossref","unstructured":"Mark Aagaard and Miriam Leeser, \u201cA formally verified system for logic synthesis,\u201dInternational Conference on Computer Design, IEEE, October 1991.","DOI":"10.1109\/ICCD.1991.139915"},{"key":"BF01607881_CR39","doi-asserted-by":"crossref","unstructured":"R.K. Brayton, R. Rudell, et al., \u201cMIS: A multiple-level logic optimization system,\u201dIEEE Transactions on Computer-Aided Design, vol. CAD-6, 1987.","DOI":"10.1109\/TCAD.1987.1270347"},{"key":"BF01607881_CR40","unstructured":"G. Hachtel, R. Jacoby, K. Keutzer and C. Morrison, \u201cOn the relationship between area optimization and multifault testability of multilevel logic,\u201dInternational Conference on Computer Aided Design, pp. 316\u2013319, ACM\/IEEE, 1989."},{"key":"BF01607881_CR41","first-page":"284","volume-title":"FPGAs","author":"W. Luk","year":"1991","unstructured":"W. Luk and I. Page, \u201cParametrising designs for Field-Programmable Gate Arrays,\u201d W. Moore and W. Luk, eds., FPGAs, pp. 284\u2013295, Abingdon: EE & CS Books, 1991."}],"updated-by":[{"DOI":"10.1007\/bf01608541","type":"correction","label":"Correction","source":"publisher","updated":{"date-parts":[[1993,12,1]],"date-time":"1993-12-01T00:00:00Z","timestamp":754704000000}}],"container-title":["Journal of VLSI signal processing systems for signal, image and video technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF01607881.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/BF01607881\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF01607881","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,31]],"date-time":"2024-12-31T19:38:50Z","timestamp":1735673930000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/BF01607881"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1993,8]]},"references-count":41,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1993,8]]}},"alternative-id":["BF01607881"],"URL":"https:\/\/doi.org\/10.1007\/bf01607881","relation":{},"ISSN":["0922-5773"],"issn-type":[{"value":"0922-5773","type":"print"}],"subject":[],"published":{"date-parts":[[1993,8]]}}}