{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,6]],"date-time":"2022-04-06T03:46:42Z","timestamp":1649216802345},"reference-count":12,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[1993,1,1]],"date-time":"1993-01-01T00:00:00Z","timestamp":725846400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J VLSI Sign Process Syst Sign Image Video Technol"],"published-print":{"date-parts":[[1993,1]]},"DOI":"10.1007\/bf01880269","type":"journal-article","created":{"date-parts":[[2005,7,4]],"date-time":"2005-07-04T19:55:21Z","timestamp":1120506921000},"page":"21-35","source":"Crossref","is-referenced-by-count":1,"title":["A design method for on-line reconfigurable array processors"],"prefix":"10.1007","volume":"5","author":[{"given":"Jens","family":"Franzen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[1993,1,1]]},"reference":[{"key":"BF01880269_CR1","volume-title":"Error Coding for Arithmetic Processors","author":"T.R.N. Rao","year":"1974","unstructured":"T.R.N. Rao, Error Coding for Arithmetic Processors, London: Academic Press, 1974."},{"key":"BF01880269_CR2","doi-asserted-by":"crossref","first-page":"712","DOI":"10.1109\/PROC.1986.13533","volume":"74","author":"M.G. Sami","year":"1986","unstructured":"M.G. Sami and R. Steffanelli, \u201cReconfigurable architectures for VLSI processing arrays,\u201dProceedings of the IEEE, vol. 74, 1986, pp. 712\u2013722.","journal-title":"Proceedings of the IEEE"},{"key":"BF01880269_CR3","doi-asserted-by":"crossref","first-page":"30","DOI":"10.1117\/12.942043","volume":"827","author":"F.T. Luk","year":"1978","unstructured":"F.T. Luk and E.K. Torng, \u201cFault tolerance for systolic arrays,\u201d InSPIE Real Time Signal Processing, vol. 827, 1978, pp. 30\u201336.","journal-title":"SPIE Real Time Signal Processing"},{"key":"BF01880269_CR4","volume-title":"Fault Tolerant Computing\u2014Theory and Techniques, vol. I","year":"1986","unstructured":"Dhiraj K. Pradhan, ed.,Fault Tolerant Computing\u2014Theory and Techniques, vol. I, Englewood Cliffs, NJ: Prentice Hall, 1986."},{"key":"BF01880269_CR5","volume-title":"VLSI Array Processors","author":"S.Y. Kung","year":"1988","unstructured":"S.Y. Kung,VLSI Array Processors, Englewood Cliffs, NJ: Prentice Hall, 1988."},{"key":"BF01880269_CR6","doi-asserted-by":"crossref","first-page":"259","DOI":"10.1109\/5.4402","volume":"76","author":"S.K. Rao","year":"1988","unstructured":"S.K. Rao and T. Kailath, \u201cRegular iterative algorithms and their implementation on processor arrays,\u201dProceedings of the IEEE, vol. 76, 1988, pp. 259\u2013269.","journal-title":"Proceedings of the IEEE"},{"key":"BF01880269_CR7","doi-asserted-by":"crossref","first-page":"33","DOI":"10.1109\/TCAD.1987.1270243","volume":"CAD-6","author":"D.I. Moldovan","year":"1987","unstructured":"D.I. Moldovan, \u201cADVIS: A software package for the design of systolic arrays,\u201dIEEE Transactions on Computer-Aided Design, vol. CAD-6, 1987, pp. 33\u201340.","journal-title":"IEEE Transactions on Computer-Aided Design"},{"key":"BF01880269_CR8","doi-asserted-by":"crossref","unstructured":"J. Franzen, \u201cDesign of run-time fault-tolerant arrays of self-checking processing elements,\u201d InApplication Specific Array Processors, 1990, pp. 168\u2013179.","DOI":"10.1109\/ASAP.1990.145453"},{"key":"BF01880269_CR9","unstructured":"M.S. Lam and H.T. Kung, \u201cFault tolerance and two-level pipelining in VLSI systolic arrays,\u201d InProc. 1984 Conference on Advanced Research in VLSI, 1984, pp. 74\u201383."},{"key":"BF01880269_CR10","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-642-45638-1","volume-title":"Boolean Functions with Engineering Applications and Computer Programs","author":"W. Schneewei\u00df","year":"1989","unstructured":"W. Schneewei\u00df,Boolean Functions with Engineering Applications and Computer Programs, Heidelberg: Springer, 1989."},{"key":"BF01880269_CR11","unstructured":"L. Thiele, \u201cOn the design of piecewise regular procesor arrays,\u201d InProc. ISCAS 89, 1989."},{"key":"BF01880269_CR12","volume-title":"Standard cell design of a fault-tolerant array-multiplier","author":"Bernd Schmale","year":"1989","unstructured":"Bernd Schmale, Standard cell design of a fault-tolerant array-multiplier (in German), Master's thesis, University of Hannover, FRG, 1989."}],"container-title":["Journal of VLSI signal processing systems for signal, image and video technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF01880269.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/BF01880269\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF01880269","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,9]],"date-time":"2019-05-09T23:07:49Z","timestamp":1557443269000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/BF01880269"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1993,1]]},"references-count":12,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1993,1]]}},"alternative-id":["BF01880269"],"URL":"https:\/\/doi.org\/10.1007\/bf01880269","relation":{},"ISSN":["0922-5773"],"issn-type":[{"value":"0922-5773","type":"print"}],"subject":[],"published":{"date-parts":[[1993,1]]}}}