{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,31]],"date-time":"2025-10-31T19:47:40Z","timestamp":1761940060075,"version":"build-2065373602"},"reference-count":37,"publisher":"Springer Science and Business Media LLC","issue":"1-2","license":[{"start":{"date-parts":[[1995,1,1]],"date-time":"1995-01-01T00:00:00Z","timestamp":788918400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of VLSI Signal Processing"],"published-print":{"date-parts":[[1995,1]]},"DOI":"10.1007\/bf02406472","type":"journal-article","created":{"date-parts":[[2006,5,12]],"date-time":"2006-05-12T02:04:18Z","timestamp":1147399458000},"page":"89-104","source":"Crossref","is-referenced-by-count":27,"title":["PHIDEO: High-level synthesis for high throughput applications"],"prefix":"10.1007","volume":"9","author":[{"given":"J. L.","family":"Van Meerbergen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P. E. R.","family":"Lippens","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"W. F. J.","family":"Verhaegh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Van Der Werf","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[1995,1,1]]},"reference":[{"key":"BF02406472_CR1","doi-asserted-by":"crossref","first-page":"201","DOI":"10.1007\/BF01581296","volume":"5","author":"J.L. Meerbergen van","year":"1993","unstructured":"J.L. van Meerbergen, P.E.R. Lippens, B. McSweeney, W.F.J. Verhaegh, A. van der Werf, and A. van Zanten, \u201cArchitectural Strategies For High-Throughput Applications,\u201dJournal of VLSI Signal Processing, Vol. 5, pp. 201\u2013220, 1993.","journal-title":"Journal of VLSI Signal Processing"},{"key":"BF02406472_CR2","doi-asserted-by":"crossref","unstructured":"D.J. Mallon and P.B. Denyer, \u201cA New Approach To Pipeline Optimisation,\u201dProceedings of the EDAC, Glasgow, March 1990, pp. 83\u201388.","DOI":"10.1109\/EDAC.1990.136625"},{"key":"BF02406472_CR3","unstructured":"P.N. Hilfinger, \u201cA high-level language and silicon compiler for digital signal processing,\u201dProceedings of the Custom Integrated Circuits Conference, May 1985."},{"key":"BF02406472_CR4","doi-asserted-by":"crossref","unstructured":"M.C. McFarland, A. Parker and R. Camposano, \u201cThe High-Level Synthesis of Digital Systems,\u201dProceedings of the IEEE, 1990, pp. 301\u2013318.","DOI":"10.1109\/5.52214"},{"key":"BF02406472_CR5","first-page":"204","volume-title":"Silicon Compilation","author":"R.K. Brayton","year":"1988","unstructured":"R.K. Brayton, R. Camposano, G. DeMicheli, R. Otten and J. van Eijndhoven, \u201cThe Yorktown Silicon Compiler\u201d in D. D. Gajski, Ed.Silicon Compilation, Reading, MA:Addison-Wesley, 1988, pp. 204\u2013311."},{"key":"BF02406472_CR6","doi-asserted-by":"crossref","first-page":"203","DOI":"10.1145\/37888.37919","volume-title":"Proceedings of the 24th Design Automation Conference","author":"F.D. Brewer","year":"1987","unstructured":"F.D. Brewer and D.D. Gajski, \u201cKnowledge Based Control in Micro-Architecture Design,\u201dProceedings of the 24th Design Automation Conference, New York, NY:ACM\/IEEE, June 1987, pp. 203\u2013209."},{"key":"BF02406472_CR7","first-page":"271","volume-title":"Proceedings of the 23rd Design Automation Conference","author":"P. Marwedel","year":"1986","unstructured":"P. Marwedel, \u201cA new synthesis algorithm for the MIMOLA software system,\u201dProceedings of the 23rd Design Automation Conference, New York, NY:ACM\/IEEE, June 1986, pp. 271\u2013277."},{"key":"BF02406472_CR8","first-page":"263","volume-title":"Proceedings of the 23rd Design Automation Conference","author":"P.G. Paulin","year":"1986","unstructured":"P.G. Paulin, J.P. Knight and E.F. Girczyc, \u201cHAL: A Multi-Paradigm Approach to Automatic Datapath Synthesis,\u201dProceedings of the 23rd Design Automation Conference, New York, NY:ACM\/IEEE, June 1986, pp. 263\u2013270."},{"key":"BF02406472_CR9","unstructured":"L. Stok and R. van den Born, \u201cEASY: Multiprocessor Architecture optimization,\u201dProc. of the Int. Workshop on Logic and Architecture Synthesis for Silicon Compilers, Grenoble, May 25\u201327 1988, pp. 1\u201315."},{"key":"BF02406472_CR10","first-page":"337","volume-title":"Proceedings of the 25th Design Automation Conference","author":"D. E. Thomas","year":"1988","unstructured":"D. E. Thomas, E. M. Dirkes, R. A. Walker, J. V. Rajan, J.A. Nestor, and R.L. Blackburn, \u201cThe System Architect's Workbench,\u201d inProceedings of the 25th Design Automation Conference, New York, NY:ACM\/IEEE, June 1988, pp. 337\u2013343."},{"key":"BF02406472_CR11","doi-asserted-by":"crossref","first-page":"259","DOI":"10.1109\/TCAD.1987.1270270","volume":"CAD-6","author":"H. Trickey","year":"1987","unstructured":"H. Trickey \u201cFlamel: A High-Level Hardware Compiler,\u201dIEEE Transactions on CAD, Vol. CAD-6, 1987, pp. 259\u2013269.","journal-title":"IEEE Transactions on CAD"},{"key":"BF02406472_CR12","doi-asserted-by":"crossref","first-page":"249","DOI":"10.1109\/30.44278","volume":"35","author":"A.H.M. Roermund van","year":"1989","unstructured":"A.H.M. van Roermund, P.J. Snijder, H. Dijkstra, C.G. Hemeryck, C. M. Huizer, J.M.P. Schmitz and R.J. Sluijter, \u201cA General-Purpose Programmable Video Signal Processor,\u201dIEEE Transactions on Consumer Electronics, Vol. 35, 1989, pp. 249\u2013258.","journal-title":"IEEE Transactions on Consumer Electronics"},{"key":"BF02406472_CR13","doi-asserted-by":"crossref","unstructured":"A.E. Casavant, M.A. D'Abreu, M. Dragomirecky, D.A. Duff, J.R. Jasica, M. J. Hartman, K. S. Hwang and W. D. Smith, \u201cA Synthesis Environment for Designing DSP Systems,\u201dIEEE Design and Test of Computers, 1989, pp. 35\u201344.","DOI":"10.1109\/54.19133"},{"key":"BF02406472_CR14","doi-asserted-by":"crossref","unstructured":"H. De Man, F. Catthoor, G. Goossens, J. Vanhoof, J. van Meerbergen and J. Huisken, \u201cArchitecture-driven synthesis techniques for VLSI implementation of DSP algorithms,Proceedings of the IEEE, 1990, pp. 319\u2013335.","DOI":"10.1109\/5.52215"},{"key":"BF02406472_CR15","doi-asserted-by":"crossref","first-page":"426","DOI":"10.1109\/4.18604","volume":"24","author":"B. Haroun","year":"1989","unstructured":"B. Haroun and M. Elmasry, \u201cSPAID: An Architectural Synthesis Tool for DSP Custom Applications,\u201dIEEE Journal of Solid State Circuits, Vol. 24, 1989, pp. 426\u2013435.","journal-title":"IEEE Journal of Solid State Circuits"},{"key":"BF02406472_CR16","volume-title":"VLSI Signal processing II","author":"J. Schuck","year":"1986","unstructured":"J. Schuck, M. Glesner and M. Lacken, \u201cFirst results and design experience with silicon Compiler ALGIC,\u201dVLSI Signal processing II, New York, IEEE Press, 1986."},{"key":"BF02406472_CR17","doi-asserted-by":"crossref","unstructured":"R. Woudsma, F. Beenker, J. van Meerbergen and C. Niessen, \u201cPiramid: an architecture-driven silicon compiler for complex DSP applications,\u201dProceedings IEEE International Symposium on Circuits and Systems, 1990, pp. 2696\u20132700.","DOI":"10.1109\/ISCAS.1990.112540"},{"key":"BF02406472_CR18","doi-asserted-by":"crossref","unstructured":"M. Potkonjak and J. Rabaey, \u201cA Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs,\u201dProc. of the Design Automation Conference, June 1989, pp. 7\u201312.","DOI":"10.1145\/74382.74385"},{"key":"BF02406472_CR19","doi-asserted-by":"crossref","unstructured":"J. Rabaey and M. Potkonjak, \u201cResource Driven Synthesis in the HYPER System,\u201dProc. of the ISCAS, New Orleans, May, 1990, pp. 2592\u20132595.","DOI":"10.1109\/ISCAS.1990.112539"},{"key":"BF02406472_CR20","doi-asserted-by":"crossref","unstructured":"P. Lippens, J. van Meerbergen, A. van der Werf, W. Verhaegh, B. McSweeney, J. Huisken and O. McArdle, \u201cPhideo: a silicon compiler for high speed algorithms,\u201dProceedings European Conference on Design Automation, Amsterdam (Netherlands), February 1991, pp. 436\u2013441.","DOI":"10.1109\/EDAC.1991.206442"},{"key":"BF02406472_CR21","doi-asserted-by":"crossref","unstructured":"Th. Krol, J. van Meerbergen, C. Niessen, Smits W. and J. Huisken, \u201cThe SPRITE Input Language: An intermediate format for High Level Synthesis,\u201dProceedings of the European Design Automation Conference (EDAC), Brussels, Belgium, March 1992, pp. 186\u2013192.","DOI":"10.1109\/EDAC.1992.205920"},{"key":"BF02406472_CR22","doi-asserted-by":"crossref","unstructured":"C.E. Leiserson, F.M. Rose and J.B. Saxe, \u201cOptimizing Synchronous Circuitry by Retiming,\u201dThird Caltech Conference on Very Large Scale Integration, 1983.","DOI":"10.1007\/978-3-642-95432-0_7"},{"key":"BF02406472_CR23","unstructured":"A. van der Werf, B. McSweeney, J. van Meerbergen, P. Lippens and W. Verhaegh, \u201cHierarchical retiming including pipelining,\u201dProceedings International Conference on VLSI (VLSI-91), Glasgow (U.K.), August 1991, pp. 11.2.1\u201311.2.10."},{"key":"BF02406472_CR24","doi-asserted-by":"crossref","unstructured":"S. Note, F. Catthoor, G. Goossens and H. De Man, \u201cCombined hardware selection and pipelining in high-performance data-path design,\u201dProceedings of the International Conference on Computer Design, Port Chester, NY, Oct. 1990, pp. 328\u2013331.","DOI":"10.1109\/ICCD.1990.130241"},{"key":"BF02406472_CR25","doi-asserted-by":"crossref","unstructured":"A. van der Werf, B. McSweeney, J. van Meerbergen, P. Lippens and W. Verhaegh, \u201cFlexible Datapath Compilation for Phideo,\u201dProceedings of the Euro ASIC Conference, Paris, May 1991, pp. 178\u2013183.","DOI":"10.1109\/EUASIC.1991.212870"},{"key":"BF02406472_CR26","doi-asserted-by":"crossref","first-page":"447","DOI":"10.1109\/43.75628","volume":"10","author":"C.B. Shung","year":"1991","unstructured":"C.B. Shung, R. Jain, K. Rimey, E. Wang, M.B. Srivastava, B. C. Richards, E. Lettang, S.K. Azim, L. Thon, P.N. Hilfinger, J.M. Rabaey and R. W. Broderson, \u201cAn Integrated CAD System for Algorithm-Specific IC Design,\u201dIEEE Transactions on CAD, Vol. 10, 1991, pp. 447\u2013482.","journal-title":"IEEE Transactions on CAD"},{"key":"BF02406472_CR27","doi-asserted-by":"crossref","DOI":"10.1109\/ICCAD.1992.279358","volume-title":"Area Optimization of Multi-Functional Processing Units","author":"A. Werf van der","year":"1992","unstructured":"A. van der Werf, E.H.L. Aarts, M.J.A. Peek, J.L. van Meerbergen, P.E.R. Lippens and W.F.J. Verhaegh, \u201cArea Optimization of Multi-Functional Processing Units,\u201d ICCAD, Santa Clara, Nov. 1992."},{"key":"BF02406472_CR28","doi-asserted-by":"crossref","unstructured":"W. Verhaegh, E. Aarts, J. Korst and P. Lippens, \u201cImproved force-directed scheduling,\u201dProceedings European Design Automation Conference, Amsterdam (Netherlands), February 1991, pp. 430\u2013435.","DOI":"10.1109\/EDAC.1991.206441"},{"key":"BF02406472_CR29","doi-asserted-by":"crossref","unstructured":"P.G. Paulin and J.P. Knight, \u201cForce-Directed Scheduling for the Behavioral Synthesis of ASICs,\u201dIEEE Transactions on CAD, Vol. 8, 1989.","DOI":"10.1109\/43.31522"},{"key":"BF02406472_CR30","doi-asserted-by":"crossref","unstructured":"P. Lippens, J. van Meerbergen, A. van der Werf, W. Verhaegh and B. McSweeney, \u201cMemory synthesis for high speed DSP applications,\u201dProceedings IEEE Custom Integrated Circuits Conference, (CICC-91), San Diego (Calif., U.S.A.), May 1991, pp. 11.7.1\u201311.7.4.","DOI":"10.1109\/CICC.1991.164138"},{"key":"BF02406472_CR31","doi-asserted-by":"crossref","first-page":"536","DOI":"10.1109\/43.3188","volume":"7","author":"M. Balakrishnan","year":"1987","unstructured":"M. Balakrishnan et al., \u201cAllocation of Multiport Memories in Data Path Synthesis,\u201dIEEE Trans. on CAD, Vol. 7, 1987, pp 536\u201340.","journal-title":"IEEE Trans. on CAD"},{"key":"BF02406472_CR32","doi-asserted-by":"crossref","unstructured":"Chien-In Henry Chen and G.E. Sobelman, \u201cSingle-port\/Multiport Memory Synthesis in Data Path Design,\u201dProceedings of the ISCAS, New Orleans, Louisiana, USA, May 1\u20133 1990, pp. 1110\u20131113.","DOI":"10.1109\/ISCAS.1990.112310"},{"key":"BF02406472_CR33","doi-asserted-by":"crossref","unstructured":"L. Stok, \u201cInterconnect Optimisation during Data Path Allocation,\u201dProc. of the European Design Automation Conference, Glasgow, March 1990, pp. 141\u2013145.","DOI":"10.1109\/EDAC.1990.136635"},{"key":"BF02406472_CR34","doi-asserted-by":"crossref","unstructured":"J.L. van Meerbergen, P.E.R. Lippens, W.F.J. Verhaegh and A. van der Werf, \u201cRelative Location Assignment for Repetitive Schedules,\u201d Proceedings of the European Conference on Design Automation with the European Event in ASIC Design, Paris, 1993, pp. 403\u2013407.","DOI":"10.1109\/EDAC.1993.386442"},{"key":"BF02406472_CR35","doi-asserted-by":"crossref","unstructured":"D.M. Grant, P.B. Denyer and I. Finlay, \u201cSynthesis of Address generators,\u201dProceedings of the IEEE Conference on Computer Aided Design, Santa Clara, CA, Nov. 1989, pp. 116\u2013119.","DOI":"10.1109\/ICCAD.1989.76917"},{"key":"BF02406472_CR36","doi-asserted-by":"crossref","unstructured":"D.M. Grant and P.B. Denyer, \u201cAddress Generation for Array Access Based on Modulus m Counters,\u201dProceedings European Conference on Design Automation, Amsterdam 1991, pp. 118\u2013122.","DOI":"10.1109\/EDAC.1991.206373"},{"key":"BF02406472_CR37","doi-asserted-by":"crossref","unstructured":"F. Beenker et al., \u201cA testability strategy for silicon-compilers,\u201d Proc. International Test Conference, pp. 660\u2013669, Washington DC, August 1989.","DOI":"10.1109\/TEST.1989.82353"}],"container-title":["Journal of VLSI signal processing systems for signal, image and video technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF02406472.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/BF02406472\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF02406472","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,8]],"date-time":"2025-01-08T22:58:49Z","timestamp":1736377129000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/BF02406472"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,1]]},"references-count":37,"journal-issue":{"issue":"1-2","published-print":{"date-parts":[[1995,1]]}},"alternative-id":["BF02406472"],"URL":"https:\/\/doi.org\/10.1007\/bf02406472","relation":{},"ISSN":["0922-5773"],"issn-type":[{"type":"print","value":"0922-5773"}],"subject":[],"published":{"date-parts":[[1995,1]]}}}