{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,11]],"date-time":"2025-01-11T05:19:55Z","timestamp":1736572795441,"version":"3.32.0"},"reference-count":22,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[1989,9,1]],"date-time":"1989-09-01T00:00:00Z","timestamp":620611200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J VLSI Sign Process Syst Sign Image Video Technol"],"published-print":{"date-parts":[[1989,9]]},"DOI":"10.1007\/bf02427794","type":"journal-article","created":{"date-parts":[[2006,7,31]],"date-time":"2006-07-31T05:06:32Z","timestamp":1154322392000},"page":"189-207","source":"Crossref","is-referenced-by-count":23,"title":["An efficient bit-level systolic cell design for finite ring digital signal processing applications"],"prefix":"10.1007","volume":"1","author":[{"given":"G. A.","family":"Jullien","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P. D.","family":"Bird","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J. T.","family":"Carr","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Taheri","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"W. C.","family":"Miller","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[1989,9,1]]},"reference":[{"key":"BF02427794_CR1","doi-asserted-by":"crossref","unstructured":"P.R. Capello, and K. Steiglitz. Digital signal processing applications of systolic algorithms. InVLSI Systems and Computations, H.T. Kung, R. Sproull and G. Steele eds., Computer Science Press, 1981, pp. 245\u2013254.","DOI":"10.1007\/978-3-642-68402-9_27"},{"issue":"6","key":"BF02427794_CR2","doi-asserted-by":"crossref","first-page":"241","DOI":"10.1049\/el:19820166","volume":"18","author":"J.V. McCanny","year":"1982","unstructured":"J.V. McCanny, and J.G. McWhirter. Implementation of signal processing functions using 1-bit systolic arrays.Electronics Letters, Vol. 18, No. 6, March 1982, pp. 241.","journal-title":"Electronics Letters"},{"key":"BF02427794_CR3","unstructured":"A. Corry, and K. Patel. Architecture of a CMOS correlator.Int. Conf on Circuits and Systems, 1983, pp. 522\u2013525."},{"issue":"4","key":"BF02427794_CR4","first-page":"125","volume":"130","author":"J.V. McCanny","year":"1983","unstructured":"J.V. McCanny and J.G. McWhirter. Bit-level systolic array circuit for matrix vector multiplication.IEE Proceedings, Vol. 130, Pt. G, No. 4, August 1983, pp. 125\u2013130.","journal-title":"IEE Proceedings"},{"issue":"6","key":"BF02427794_CR5","first-page":"632","volume":"131","author":"J.V. McCanny","year":"1984","unstructured":"J.V. McCanny and J.G. McWhirter. Optimized bit level systolic array for convolution.IEE Proceedings, Vol. 131, Pt. G, No. 6, October 1984, pp. 632\u2013637.","journal-title":"IEE Proceedings"},{"key":"BF02427794_CR6","unstructured":"K. Iwano, and K. Steiglitz. Some experiments in leaf-cell optimization. InVLSI Signal Processing, IEEE Press, 1985, pp. 387\u2013395."},{"key":"BF02427794_CR7","doi-asserted-by":"crossref","unstructured":"M. Hatamian, and G.L. Cash. High speed signal processing, pipelining, and signal processing.Int. Conf. on Acoustics, Speech, and Signal Processing, April 1986, pp. 1173\u20131176.","DOI":"10.1109\/ICASSP.1986.1168842"},{"issue":"10","key":"BF02427794_CR8","doi-asserted-by":"crossref","first-page":"461","DOI":"10.1016\/0141-9331(83)90533-1","volume":"7","author":"S. Y. Kung","year":"1983","unstructured":"S. Y. Kung and J. Annevelink. VLSI design for massively parallel signal processors.Microprocessors and Microsystems, Vol. 7, No. 10, December 1983, pp. 461\u2013467.","journal-title":"Microprocessors and Microsystems"},{"key":"BF02427794_CR9","doi-asserted-by":"crossref","unstructured":"S.C. Knowles, R.E Woods, J.G. McWhirter, and J.V. McCanny. Bit-level systolic arrays for IIR filtering.International Conference on Systolic Arrays, San Diego, May 1988, pp. 653\u2013663.","DOI":"10.1109\/ARRAYS.1988.18102"},{"key":"BF02427794_CR10","volume-title":"Systolic Arrays","author":"S. Bandyopadhyay","year":"1986","unstructured":"S. Bandyopadhyay, G.A. Jullien, and M. Bayoumi. Systolic arrays over finite rings with applications to digital signal processing. InSystolic Arrays, edited by W. Moore, A. McCabe, and R. Urquhart, Adam Hilger, Bristol, 1986."},{"key":"BF02427794_CR11","unstructured":"M.A. Bayoumi, G.A. Jullien, and W.C. Miller. Bit-Parallel based filters using residue number systems.27th Midwest Symposium on Circuits and Systems, June 1984."},{"key":"BF02427794_CR12","volume-title":"Residue Arithmetic and its Applications to Computer Technology","author":"N.S. Szabo","year":"1967","unstructured":"N.S. Szabo and R.I. Tanaka.Residue Arithmetic and its Applications to Computer Technology. McGraw-Hill, New York, 1967."},{"issue":"1","key":"BF02427794_CR13","doi-asserted-by":"crossref","first-page":"37","DOI":"10.1109\/MC.1982.1653825","volume":"15","author":"H.T. Kung","year":"1982","unstructured":"H.T. Kung. Why systolic architectures.IEEE Computer Magazine, Vol. 15, No. 1, January 1982, pp. 37\u201346.","journal-title":"IEEE Computer Magazine"},{"issue":"1","key":"BF02427794_CR14","doi-asserted-by":"crossref","first-page":"113","DOI":"10.1109\/PROC.1983.12532","volume":"71","author":"D.I. Moldovan","year":"1983","unstructured":"D.I. Moldovan. On the design of algorithms for VLSI systolic arrays.Proc. of IEEE, Vol. 71, No. 1, January 1983, pp. 113\u2013120.","journal-title":"Proc. of IEEE"},{"issue":"3","key":"BF02427794_CR15","doi-asserted-by":"crossref","first-page":"504","DOI":"10.1109\/49.1918","volume":"6","author":"M. Taheri","year":"1988","unstructured":"M. Taheri, G.A. Jullien, and W.C. Miller. High speed signal processing using systolic arrays over finite rings.IEEE Trans. on Selected Areas in Communications, VLSI in Communications III, Vol. 6, No. 3, April 1988, pp. 504\u2013512.","journal-title":"IEEE Trans. on Selected Areas in Communications, VLSI in Communications III"},{"issue":"10","key":"BF02427794_CR16","doi-asserted-by":"crossref","first-page":"540","DOI":"10.1049\/el:19860368","volume":"22","author":"J.V. McCanny","year":"1986","unstructured":"J.V. McCanny, R.A. Evans, and J.G. McWhirter. Use of unidirectional data flow in bit level systolic array chips.Electronics letters, Vol. 22, No. 10, May 1986, pp. 540\u2013541.","journal-title":"Electronics letters"},{"key":"BF02427794_CR17","unstructured":"G.A. Jullien and W.C. Miller. The design of 1-bit systolic cells and arrays for high speed computational throughput. In preparation, 1988."},{"key":"BF02427794_CR18","volume-title":"Theory and Application of Digital Signal Processing","author":"L.R. Rabiner","year":"1975","unstructured":"L.R. Rabiner and B. Gold.Theory and Application of Digital Signal Processing. Prentice-Hall, Englewood Cliffs, N.J., 1975."},{"issue":"6","key":"BF02427794_CR19","doi-asserted-by":"crossref","first-page":"456","DOI":"10.1109\/TASSP.1974.1162619","volume":"ASSP-22","author":"A. Peled","year":"1974","unstructured":"A. Peled and B. Liu. A new hardware realization of digital filters.IEEE Trans. on Acoustic, Speech, and Signal Processing, Vol. ASSP-22, No. 6, December 1974, pp. 456\u2013462.","journal-title":"IEEE Trans. on Acoustic, Speech, and Signal Processing"},{"key":"BF02427794_CR20","unstructured":"M. Taheri.VLSI Fault-Tolerant Systolic Architectures. Ph.D. dissertation, University of Windsor, April 1988."},{"key":"BF02427794_CR21","unstructured":"G.A. Jullien, M. Taheri, and W.C. Miller. A low-overhead scheme for testing a bit level finite ring systolic array. Submitted for publication,Journal of VLSI Signal Processing, 1988."},{"key":"BF02427794_CR22","unstructured":"M. Taheri, G.A. Jullien, and W.C. Miller. Fault detection in distributed RNS processing.IEEE Inter. Conf. on Computer Design: VLSI in Computers & Processors, October 1987, pp. 302\u2013305."}],"container-title":["Journal of VLSI signal processing systems for signal, image and video technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF02427794.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/BF02427794\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF02427794","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,10]],"date-time":"2025-01-10T07:57:28Z","timestamp":1736495848000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/BF02427794"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1989,9]]},"references-count":22,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1989,9]]}},"alternative-id":["BF02427794"],"URL":"https:\/\/doi.org\/10.1007\/bf02427794","relation":{},"ISSN":["0922-5773"],"issn-type":[{"type":"print","value":"0922-5773"}],"subject":[],"published":{"date-parts":[[1989,9]]}}}