{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,2]],"date-time":"2022-04-02T19:10:55Z","timestamp":1648926655052},"reference-count":15,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[1997,4,1]],"date-time":"1997-04-01T00:00:00Z","timestamp":859852800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Algorithmica"],"published-print":{"date-parts":[[1997,4]]},"DOI":"10.1007\/bf02523682","type":"journal-article","created":{"date-parts":[[2006,11,8]],"date-time":"2006-11-08T04:50:25Z","timestamp":1162961425000},"page":"426-448","source":"Crossref","is-referenced-by-count":0,"title":["New algorithms for minimizing the longest wire length during circuit compaction"],"prefix":"10.1007","volume":"17","author":[{"given":"S. E.","family":"Hambrusch","sequence":"first","affiliation":[]},{"given":"Hung-Yi","family":"Tu","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"BF02523682_CR1","volume-title":"Introduction to Algorithms","author":"T. H. Cormen","year":"1990","unstructured":"T. H. Cormen, C. E. Leiserson, and R. L. Rivest,Introduction to Algorithms. MIT Press, Cambridge, MA, 1990."},{"key":"BF02523682_CR2","doi-asserted-by":"crossref","unstructured":"S. Gao, M. Kaufmann, and F. M. Maley. Advances in homotopic layout compaction.Proceedings of the 1989ACM Symposium on Parallel Algorithms and Architectures, pages 273\u2013282, 1989.","DOI":"10.1145\/72935.72964"},{"issue":"2","key":"BF02523682_CR3","doi-asserted-by":"crossref","first-page":"113","DOI":"10.1016\/0167-9260(92)90023-R","volume":"14","author":"S. E. Hambrusch","year":"1992","unstructured":"S. E. Hambrusch and H. Y. Tu, Minimizing total wire length during 1-dimensional compaction.INTEGRATION, the VLSI Journal, 14(2):113\u2013144, 1992.","journal-title":"INTEGRATION, the VLSI Journal"},{"issue":"12","key":"BF02523682_CR4","doi-asserted-by":"crossref","first-page":"1495","DOI":"10.1109\/43.180263","volume":"11","author":"J. F. Lee","year":"1992","unstructured":"J. F. Lee and C. K. Wong. A performance-aimed cell compactor with automatic jogs.IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 11(12):1495\u20131507, December 1992.","journal-title":"IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems"},{"key":"BF02523682_CR5","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-322-92106-2","volume-title":"Combinatorial Algorithms for Integrated Circuit Layout","author":"T. Lengauer","year":"1990","unstructured":"T. Lengauer,Combinatorial Algorithms for Integrated Circuit Layout. Wiley, New York, 1990."},{"issue":"2","key":"BF02523682_CR6","doi-asserted-by":"crossref","first-page":"62","DOI":"10.1109\/TCAD.1983.1270022","volume":"2","author":"Y. Z. Liao","year":"1983","unstructured":"Y. Z. Liao and C. K. Wong. An algorithm to compact a VLSI symbolic layout with mixed constraints.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2(2):62\u201369, April 1983.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"BF02523682_CR7","doi-asserted-by":"crossref","unstructured":"D. Marple. A hierarchy preserving hierarchical compactor.Proceedings of the 27th ACM\/IEEE Design Automation Conference, pages 375\u2013381, 1990.","DOI":"10.1145\/123186.123311"},{"issue":"4","key":"BF02523682_CR8","doi-asserted-by":"crossref","first-page":"759","DOI":"10.1137\/0212052","volume":"12","author":"N. Megiddo","year":"1983","unstructured":"N. Megiddo. Linear-time algorithms for linear programming inR 3 and related problems.SIAM Journal on Computing, 12(4):759\u2013775, November 1983.","journal-title":"SIAM Journal on Computing"},{"key":"BF02523682_CR9","first-page":"199","volume-title":"Layout Design and Verification","author":"D. A. Mlynski","year":"1986","unstructured":"D. A. Mlynski and C. H. Sung. Layout compaction. In T. Ohtsuki, editor,Layout Design and Verification, pages 199\u2013235, Elsevier, Amsterdam, 1986."},{"key":"BF02523682_CR10","doi-asserted-by":"crossref","first-page":"65","DOI":"10.1007\/978-94-009-3649-2_4","volume-title":"Design Systems for VLSI Circuits","author":"A. R. Newton","year":"1987","unstructured":"A. R. Newton. Symbolic layout and procedural design. In G. DeMicheli, A. Sangiovanni-Vincentelli, and P. Antognetti, editors,Design Systems for VLSI Circuits, pages 65\u2013112. Martinus Nijhoff, Boston, MA, 1987."},{"key":"BF02523682_CR11","doi-asserted-by":"crossref","unstructured":"A. Onozawa. Layout compaction with attractive and repulsive constraints.Proceedings of the 27th ACM\/IEEE Design Automation Conference, pages 369\u2013374, 1990.","DOI":"10.1145\/123186.123308"},{"key":"BF02523682_CR12","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4612-1098-6","volume-title":"Computational Geometry","author":"F. P. Preparata","year":"1985","unstructured":"F. P. Preparata and M. I. Shamos,Computational Geometry. Springer-Verlag, New York, 1985."},{"key":"BF02523682_CR13","doi-asserted-by":"crossref","unstructured":"W. L. Schiele. Improved compaction by minimized length of wires.Proceedings of the 20th ACM\/IEEE Design Automation Conference, pages 121\u2013121, 1983.","DOI":"10.1109\/DAC.1983.1585636"},{"key":"BF02523682_CR14","first-page":"259","volume-title":"Advances in Computing Research: VLSI Theory","author":"M. Schlag","year":"1984","unstructured":"M. Schlag, F. Luccio, P. Maestrini, D. T. Lee, and C. K. Wong. A visibility problem in VLSI layout compaction. In F. P. Preparata, editor,Advances in Computing Research: VLSI Theory, pages 259\u2013282. JAI Press, Greenwich, CT, 1984."},{"issue":"3","key":"BF02523682_CR15","doi-asserted-by":"crossref","first-page":"286","DOI":"10.1109\/31.1741","volume":"35","author":"B. X. Weis","year":"1988","unstructured":"B. X. Weis and D. A. Mlynski. A graph-theoretic approach to the relative placement problem.IEEE Transactions on Circuits and Systems, 35(3):286\u2013293, 1988.","journal-title":"IEEE Transactions on Circuits and Systems"}],"container-title":["Algorithmica"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF02523682.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/BF02523682\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF02523682","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,4,18]],"date-time":"2020-04-18T23:22:17Z","timestamp":1587252137000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/BF02523682"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1997,4]]},"references-count":15,"journal-issue":{"issue":"4","published-print":{"date-parts":[[1997,4]]}},"alternative-id":["BF02523682"],"URL":"https:\/\/doi.org\/10.1007\/bf02523682","relation":{},"ISSN":["0178-4617","1432-0541"],"issn-type":[{"value":"0178-4617","type":"print"},{"value":"1432-0541","type":"electronic"}],"subject":[],"published":{"date-parts":[[1997,4]]}}}