{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,1]],"date-time":"2025-02-01T05:32:12Z","timestamp":1738387932205,"version":"3.35.0"},"reference-count":23,"publisher":"Springer Science and Business Media LLC","issue":"6","license":[{"start":{"date-parts":[[2002,11,1]],"date-time":"2002-11-01T00:00:00Z","timestamp":1036108800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J. Compt. Sci. & Technol."],"published-print":{"date-parts":[[2002,11]]},"DOI":"10.1007\/bf02960763","type":"journal-article","created":{"date-parts":[[2008,9,25]],"date-time":"2008-09-25T00:59:57Z","timestamp":1222304397000},"page":"731-737","source":"Crossref","is-referenced-by-count":1,"title":["BIST design for detecting multiple stuck-open faults in CMOS circuits using transition count"],"prefix":"10.1007","volume":"17","author":[{"given":"Hafizur","family":"Rahaman","sequence":"first","affiliation":[]},{"given":"Debesh K.","family":"Das","sequence":"additional","affiliation":[]},{"given":"Bhargab B.","family":"Bhattacharya","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"BF02960763_CR1","doi-asserted-by":"crossref","first-page":"1449","DOI":"10.1002\/j.1538-7305.1978.tb02106.x","volume":"57","author":"R L Wadsack","year":"1978","unstructured":"Wadsack R L. Fault modeling and logic simulators of CMOS and MOS integrated, circuits.The Bell System Technical Journal, May\u2013June, 1978, 57: 1449\u20131479.","journal-title":"The Bell System Technical Journal"},{"key":"BF02960763_CR2","first-page":"742","volume":"35","author":"S M Reddy","year":"1986","unstructured":"Reddy S M, Reddy M K. Testable realizations of FET stuck-open faults in CMOS combinational logic circuits.IEEE TC, 1986, C-35: 742\u2013754.","journal-title":"IEEE TC"},{"key":"BF02960763_CR3","doi-asserted-by":"crossref","first-page":"42","DOI":"10.1109\/MDT.1987.295148","volume":"4","author":"D N Liu","year":"1987","unstructured":"Liu D N, McCluskey E J. Designing CMOS circuits for testability.IEEE Design & Test, 1987, 4: 42\u201349.","journal-title":"IEEE Design & Test"},{"key":"BF02960763_CR4","doi-asserted-by":"crossref","first-page":"973","DOI":"10.1109\/43.35549","volume":"8","author":"S Chakravarty","year":"1989","unstructured":"Chakravarty S. On the complexity of computing test sets for complex CMOS gates.IEEE Transactions on Computer-Aided Design, 1989, 8: 973\u2013980.","journal-title":"IEEE Transactions on Computer-Aided Design"},{"doi-asserted-by":"crossref","unstructured":"Chen C A, Gupta S K. BIST test pattern generator for stuck-open and delay testing. InProc. European Test Conference, 1994, pp.289\u2013296.","key":"BF02960763_CR5","DOI":"10.1109\/EDTC.1994.326862"},{"doi-asserted-by":"crossref","unstructured":"Nandi D, Palchaudhuri P, Roy S, Sharma M. Exhaustive two-pattern test generation with cellular automata. InProc. Asian Test Symposium, 1992, pp. 230\u2013234.","key":"BF02960763_CR6","DOI":"10.1109\/ATS.1992.224403"},{"doi-asserted-by":"crossref","unstructured":"Wang W, Gupta S K. Weighted random robust path delay testing of synthesized multi-level circuits. InProc. VLSI Test Symposium (VTS), Cherry Hill NJ, 1994, pp. 291\u2013297.","key":"BF02960763_CR7","DOI":"10.1109\/VTEST.1994.292298"},{"key":"BF02960763_CR8","doi-asserted-by":"crossref","first-page":"219","DOI":"10.1007\/BF02341826","volume":"8","author":"I Voyiatzis","year":"1996","unstructured":"Voyiatzis I, Paschallis A, Nikolos D, Halatsis C. An efficient built-in self-test method for robust path delay fault testing.Journal of Electronic Testing: Theory and Applications (JETTA), 1996, 8: 219\u2013222.","journal-title":"Journal of Electronic Testing: Theory and Applications (JETTA)"},{"unstructured":"Craig G L, Kime C R. Pseudo-exhaustive adjacency test: A BIST, approach for stuck-open faults InProc. International Test Conference (ITC), 1985, pp. 126\u2013137.","key":"BF02960763_CR9"},{"doi-asserted-by":"crossref","unstructured":"Das D K, Chaudhuri I, Bhattacharya B B. Design of an optimal test pattern generator for built-in self-testing of path delay faults. InProc. International Conference on VLSI Design, Chennai India, 1998, pp. 205\u2013210.","key":"BF02960763_CR10","DOI":"10.1109\/ICVD.1998.646603"},{"unstructured":"Bate J A, Miller D M. Exhaustive testing of stuck-open faults in CMOS combinational circuits. InIEE, Proc., pt. E, 1988, 135(1): 10\u201316.","key":"BF02960763_CR11"},{"unstructured":"Starke C W. Built-in test for CMOS circuits. InProc. ITC, 1984, pp. 309\u2013314.","key":"BF02960763_CR12"},{"key":"BF02960763_CR13","first-page":"442","volume":"29","author":"J Savir","year":"1976","unstructured":"Savir J. Syndrome testable design of combinational circuits.IEEE Transactions on Computers, Nov., 1976, C-29: 442\u2013451.","journal-title":"IEEE Transactions on Computers"},{"key":"BF02960763_CR14","doi-asserted-by":"crossref","first-page":"996","DOI":"10.1109\/12.42129","volume":"38","author":"B B Bhattacharya","year":"1989","unstructured":"Bhattacharya B B, Seth S C. Design of parity testable combinational circuits.IEEE Transactions on Computers, April, 1989, C-38: 996\u20131000.","journal-title":"IEEE Transactions on Computers"},{"key":"BF02960763_CR15","doi-asserted-by":"crossref","first-page":"1088","DOI":"10.1109\/TC.1986.1676719","volume":"35","author":"P K Lui","year":"1986","unstructured":"Lui P K, Mujio J C. Spectral signature testing of multiple stuck-at faults in irredundant combinational networks.IEEE Transactions on Computers, Dec., 1986, C-35: 1088\u20131092.","journal-title":"IEEE Transactions on Computers"},{"key":"BF02960763_CR16","doi-asserted-by":"crossref","first-page":"613","DOI":"10.1109\/TC.1976.1674661","volume":"25","author":"J P Hayes","year":"1976","unstructured":"Hayes J P. Transitions count testing of combinational circuits.IEEE Transactions on Computers, June, 1976, C-25: 613\u2013620.","journal-title":"IEEE Transactions on Computers"},{"unstructured":"Sengupta I. Index vector testing, of combinational circuits. InProc. International Test Conference, 1987, pp. 1108\u20131112.","key":"BF02960763_CR17"},{"key":"BF02960763_CR18","doi-asserted-by":"crossref","first-page":"788","DOI":"10.1109\/12.24287","volume":"38","author":"T R Damarala","year":"1989","unstructured":"Damarala T Ret al. Fault detection in combinational networks by Reed-Muller transforms.IEEE Transactions on Computers, June 1989, C-38: 788\u2013797.","journal-title":"IEEE Transactions on Computers"},{"doi-asserted-by":"crossref","unstructured":"Das D K, Chakraborty S, Bhattacharya B B. New BIST techniques for universal and robust testing of CMOS stuck-open faults. InProc. International Conference on VLSI Design, 1997, pp. 303\u2013308.","key":"BF02960763_CR19","DOI":"10.1109\/ICVD.1997.568094"},{"unstructured":"Jha N K. Detecting multiple faults in CMOS circuits. InProc. International Test Conference, 1986, pp. 514\u2013519.","key":"BF02960763_CR20"},{"doi-asserted-by":"crossref","unstructured":"Kundu S, Reddy S M. On the design of robust testable CMOS combinational logic circuits. InProc. FTCS, Tokyo, Japan, 1988, pp. 220\u2013225.","key":"BF02960763_CR21","DOI":"10.1109\/FTCS.1988.5323"},{"doi-asserted-by":"crossref","unstructured":"Kundu S, Reddy S M, Jha N K. On the design of robust testable multiple fault testable CMOS combinational logic circuits.Digest of ICCAD, 1988, pp. 240\u2013243.","key":"BF02960763_CR22","DOI":"10.1109\/ICCAD.1988.122502"},{"key":"BF02960763_CR23","doi-asserted-by":"crossref","first-page":"53","DOI":"10.1109\/4.65711","volume":"26","author":"A P Jayasumana","year":"1991","unstructured":"Jayasumana, A P, Malaya Y K, Rajsuman R. Design of CMOS circuits for stuck-open testability.IEEE Journal of Solid State Circuits, 1991, 26: 53\u201362.","journal-title":"IEEE Journal of Solid State Circuits"}],"container-title":["Journal of Computer Science and Technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF02960763.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/BF02960763\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF02960763","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,1]],"date-time":"2025-02-01T02:20:16Z","timestamp":1738376416000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/BF02960763"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,11]]},"references-count":23,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2002,11]]}},"alternative-id":["BF02960763"],"URL":"https:\/\/doi.org\/10.1007\/bf02960763","relation":{},"ISSN":["1000-9000","1860-4749"],"issn-type":[{"type":"print","value":"1000-9000"},{"type":"electronic","value":"1860-4749"}],"subject":[],"published":{"date-parts":[[2002,11]]}}}