{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,9]],"date-time":"2025-02-09T05:16:30Z","timestamp":1739078190970,"version":"3.37.0"},"reference-count":17,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[1991,6,1]],"date-time":"1991-06-01T00:00:00Z","timestamp":675734400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["New Gener Comput"],"published-print":{"date-parts":[[1991,6]]},"DOI":"10.1007\/bf03037641","type":"journal-article","created":{"date-parts":[[2009,4,24]],"date-time":"2009-04-24T03:39:07Z","timestamp":1240544347000},"page":"149-169","source":"Crossref","is-referenced-by-count":0,"title":["Locally parallel cache design based on KL1 memory access characteristics"],"prefix":"10.1007","volume":"9","author":[{"given":"Akira","family":"Matsumoto","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Takayuki","family":"Nakagawa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masatoshi","family":"Sato","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yasunori","family":"Kimura","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kenji","family":"Nishida","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Atsuhiro","family":"Goto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"4","key":"BF03037641_CR1","doi-asserted-by":"crossref","first-page":"273","DOI":"10.1145\/6513.6514","volume":"4","author":"J. Archibald","year":"1986","unstructured":"Archibald, J. and Baer, J., \u201cCache Coherence Protocols: Evaluation Using a Multiprocessor Simulation Model,\u201dACM Transaction of Computer Systems, 4, 4, pp. 273\u2013298, 1986.","journal-title":"ACM Transaction of Computer Systems"},{"key":"BF03037641_CR2","doi-asserted-by":"crossref","unstructured":"Bitar, P. and Despain, A. M., \u201cMultiprocessor Cache Synchronization,\u201d inProc. of the 13th Annual International Symposium on Computer Architecture, pp. 424\u2013433, June, 1986.","DOI":"10.1145\/17356.17405"},{"key":"BF03037641_CR3","doi-asserted-by":"crossref","unstructured":"Eggers, S. J. and Katz, R. H., \u201cA Characterization of Sharing in Parallel Programs and Its Application to Coherency Protocol Evaluation,\u201d inProc. of the 15th Annual International Symposium on Computer Architecture, pp. 373\u2013382, June, 1988.","DOI":"10.1109\/ISCA.1988.5248"},{"key":"BF03037641_CR4","doi-asserted-by":"crossref","unstructured":"Goodman, J. R., \u201cUsing Cache Memory to Reduce Processor-Memory Traffic,\u201d inProc. of the 10th Annual International Symposium on Computer Architecture, pp. 124\u2013131, 1983.","DOI":"10.1145\/800046.801647"},{"key":"BF03037641_CR5","unstructured":"Goto, A., \u201cParallel Inference Machine Research in FGCS Project,\u201d inUS-Japan AI Symposium 87, pp. 21\u201336, Nov., 1987."},{"key":"BF03037641_CR6","unstructured":"Hwang, K. and Briggs, F. A.,Computer Architecture and Parallel Processing, McGraw-Hill, 1984."},{"key":"BF03037641_CR7","doi-asserted-by":"crossref","unstructured":"Katz, R. H., Eggers, S. J., Wood, D. A., Perkins, C. L. and Sheldon, R. G., \u201cImplementing a Cache Consistency Protocol,\u201d inProc. of the 12th Annual International Symposium on Computer Architecture, pp. 276\u2013283, June, 1985.","DOI":"10.1145\/327070.327237"},{"key":"BF03037641_CR8","unstructured":"Kimura, Y. and Chikayama, T., \u201cAn Abstract KL1 Machine and Its Instruction Set,\u201d inProceedings of the 1987 Symposium on Logic Programming, pp. 468\u2013477, 1987. (also published asICOT Technical Report, TR-246)."},{"key":"BF03037641_CR9","doi-asserted-by":"crossref","unstructured":"Papamarcos, M. S. and Patel, J. H., \u201cA Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories,\u201d inProc. of the 11th Annual International Symposium on Computer Architecture, pp. 348\u2013354, 1984.","DOI":"10.1145\/800015.808204"},{"key":"BF03037641_CR10","unstructured":"Sato, M., Goto, A. et al., \u201cKL1 Execution Model for PIM Cluster with Shared Memory\u201d, inProc. of the Fourth International Conference on Logic Programming, pp. 338\u2013355, 1987."},{"key":"BF03037641_CR11","unstructured":"Sequent Computer Systems, Inc.,Balance 8000\/21000 Technical Summary, 1986."},{"issue":"3","key":"BF03037641_CR12","doi-asserted-by":"crossref","first-page":"473","DOI":"10.1145\/356887.356892","volume":"14","author":"A. J. Smith","year":"1982","unstructured":"Smith, A. J., \u201cCache Memories,\u201dComputing Surveys, 14, 3, pp. 473\u2013530, 1982.","journal-title":"Computing Surveys"},{"key":"BF03037641_CR13","doi-asserted-by":"crossref","unstructured":"Sweazey, P. and Smith, A. J., \u201cA Class of Compatible Cache Consistency Protocols and Their Support by the IEEE Futurebus,\u201d inProc. of the 13th Annual International Symposium on Computer Architecture, pp. 414\u2013423, 1986.","DOI":"10.1145\/17356.17404"},{"key":"BF03037641_CR14","doi-asserted-by":"crossref","unstructured":"Taki, K., Nakajima, K., Nakashima, H. and Ikeda, M., \u201cPerformance and Architectual Evaluation of the PSI Machine,\u201d inProc. of the Second International Conference on Architectual Support for Programming Language and Operating Systems (ASPLOS), pp. 128\u2013135, 1987.","DOI":"10.1145\/36204.36195"},{"key":"BF03037641_CR15","unstructured":"Tick, E., \u201cProlog Memory-Referencing Behavior,\u201dTechnical Report 85-281, Stanford University, 1985."},{"key":"BF03037641_CR16","doi-asserted-by":"crossref","unstructured":"Ueda, K., \u201cGuarded Horn Clauses: A Parallel Logic Programming Language with the Concept of a Guard,\u201dICOT Technical Report, TR-208, 1986. (also appeared inProgramming of Future Generation Computers, North-Holland, Amsterdam, 1988.)","DOI":"10.1007\/3-540-16479-0_17"},{"key":"BF03037641_CR17","unstructured":"Warren, D. H. D., \u201cAn Abstract Prolog Instruction Set,\u201dTechnical Note 309, Artificial Intelligence Center, SRI, 1983."}],"container-title":["New Generation Computing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF03037641.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/BF03037641\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF03037641","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,9]],"date-time":"2025-02-09T04:42:16Z","timestamp":1739076136000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/BF03037641"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1991,6]]},"references-count":17,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1991,6]]}},"alternative-id":["BF03037641"],"URL":"https:\/\/doi.org\/10.1007\/bf03037641","relation":{},"ISSN":["0288-3635","1882-7055"],"issn-type":[{"type":"print","value":"0288-3635"},{"type":"electronic","value":"1882-7055"}],"subject":[],"published":{"date-parts":[[1991,6]]}}}