{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T12:12:10Z","timestamp":1742386330783},"reference-count":23,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[1996,6,1]],"date-time":"1996-06-01T00:00:00Z","timestamp":833587200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Int J Parallel Prog"],"published-print":{"date-parts":[[1996,6]]},"DOI":"10.1007\/bf03356750","type":"journal-article","created":{"date-parts":[[2016,5,26]],"date-time":"2016-05-26T02:17:10Z","timestamp":1464229030000},"page":"235-263","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":9,"title":["A Mean Value Analysis Multiprocessor Model Incorporating Superscalar Processors and Latency Tolerating Techniques"],"prefix":"10.1007","volume":"24","author":[{"given":"David H.","family":"Albonesi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Israel","family":"Koren","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2016,5,26]]},"reference":[{"key":"BF03356750_CR1","unstructured":"D. H. Albonesi and I. Koren, An analytical model of high performance superscalar-based multiprocessors, Intl. Conf. on Parallel Architectures and Compilation Techniques, pp. 194\u2013203 (1995)."},{"key":"BF03356750_CR2","volume-title":"Quantative System Performance, Computer Analysis Using Queuing Network Models","author":"ED Lazowska","year":"1991","unstructured":"E. D. Lazowska, J. Zahorjan, G. S. Graham, and K. C. Sevcik, Quantative System Performance, Computer Analysis Using Queuing Network Models, Prentice Hall, Englewood Cliffs, New Jersey (1991)."},{"key":"BF03356750_CR3","doi-asserted-by":"crossref","unstructured":"D. Lenoski, J. Laudon, T. Joe, D. Nakahira, L. Stevens, A. Gupta, and J. Hennessy, The DASH prototype: implementation and performance, Int\u2019l. Symp. on Computer Architecture, pp. 92\u2013103 (1992).","DOI":"10.1145\/139669.139706"},{"key":"BF03356750_CR4","unstructured":"J. R. Goodman and P. J. Woest, The Wisconsin multicube: a new large-scale cache-coherent multiprocessor, Intl. Symp. on Computer Architecture, pp. 422\u2013431 (1988)."},{"key":"BF03356750_CR5","doi-asserted-by":"crossref","unstructured":"R. Jog, P. L. Vitale, and J. R. Callister, Performance evaluation of a commercial cache-coherent shared memory multiprocessor, Intl. Conf. on Measurement and Modeling of Computer Systems, pp. 173\u2013182 (1990).","DOI":"10.1145\/98460.98756"},{"key":"BF03356750_CR6","doi-asserted-by":"crossref","unstructured":"M. Chiang and G. S. Sohi, Experience with Mean Value Analysis models for evaluating shared bus, throughput-oriented multiprocessors, Intl. Conf. on Measurement and Modeling of Computer Systems, pp. 90\u2013100 (1991).","DOI":"10.1145\/107972.107982"},{"key":"BF03356750_CR7","doi-asserted-by":"crossref","unstructured":"M. K. Vernon, E. D. Lazowska, and J. Zahorjan, An accurate and efficient performance analysis technique for multiprocessor snooping cache consistency protocols, Int\u2019l. Symp. on Computer Architecture, pp. 308\u2013315 (1988).","DOI":"10.1145\/633625.52435"},{"issue":"3","key":"BF03356750_CR8","doi-asserted-by":"crossref","first-page":"297","DOI":"10.1109\/12.127442","volume":"41","author":"M Chiang","year":"1992","unstructured":"M. Chiang and G. S. Sohi, Evaluating design choices for shared bus multiprocessors in a throughput-oriented environment, IEEE Trans. on Computers, 41(3):297\u2013317 (1992).","journal-title":"IEEE Trans. on Computers"},{"key":"BF03356750_CR9","unstructured":"D. H. Albonesi and I. Koren, Tradeoffs in the design of single chip multiprocessors, Intl. Conf. on Parallel Architectures and Compilation Techniques (PACT \u201994), pp. 25\u201334 (1994)."},{"key":"BF03356750_CR10","doi-asserted-by":"crossref","unstructured":"S. T. Leutenegger and M. K. Vernon, A mean-value performance analysis of a new multiprocessor architecture, Int\u2019l. Conf. on Measurement and Modeling of Computer Systems, pp. 167\u2013176 (1988).","DOI":"10.1145\/55595.55615"},{"issue":"4","key":"BF03356750_CR11","doi-asserted-by":"crossref","first-page":"287","DOI":"10.1016\/0166-5316(89)90046-1","volume":"9","author":"MK Vernon","year":"1989","unstructured":"M. K. Vernon, R. Jog, and G. S. Sohi, Performance analysis of hierarchical cache-consistent multiprocessors, Performance Evaluation, 9(4):287\u2013302 (1989).","journal-title":"Performance Evaluation"},{"key":"BF03356750_CR12","doi-asserted-by":"crossref","unstructured":"J. Torrellas, J. Hennessy, and T. Weil, Analysis of critical architectural and program parameters in a hierarchical shared-memory multiprocessor, Int\u2019l. Conf. on Measurement and Modeling of Computer Systems, pp. 163\u2013172 (1990).","DOI":"10.1145\/98457.98754"},{"issue":"4","key":"BF03356750_CR13","doi-asserted-by":"crossref","first-page":"431","DOI":"10.1109\/12.278481","volume":"43","author":"PK Dubey","year":"1994","unstructured":"P. K. Dubey, G. B. Adams III, and M. J. Flynn, Instruction window size trade-offs and characterization of program parallelism, IEEE Trans. on Computers, 43(4):431\u2013442 (1994).","journal-title":"IEEE Trans. on Computers"},{"issue":"3","key":"BF03356750_CR14","doi-asserted-by":"crossref","first-page":"22","DOI":"10.1109\/40.216746","volume":"13","author":"T Asprey","year":"1993","unstructured":"T. Asprey, G. S. Averiii, E. DeLano, R. Mason, B. Weiner, and J. Yetter, Performance features of the PA7100 microprocessor, IEEE Micro, 13(3):22\u201335 (1993).","journal-title":"IEEE Micro"},{"issue":"3","key":"BF03356750_CR15","doi-asserted-by":"crossref","first-page":"36","DOI":"10.1109\/40.216747","volume":"13","author":"E McLellan","year":"1993","unstructured":"E. McLellan, The Alpha AXP architecture and 21064 processor, IEEE Micro, 13(3):36\u201347 (1993).","journal-title":"IEEE Micro"},{"issue":"3","key":"BF03356750_CR16","doi-asserted-by":"crossref","first-page":"11","DOI":"10.1109\/40.216745","volume":"13","author":"D Alpert","year":"1993","unstructured":"D. Alpert and D. Avnon, Architecture of the Pentium microprocessor, IEEE Micro, 13(3):11\u201321 (1993).","journal-title":"IEEE Micro"},{"issue":"4","key":"BF03356750_CR17","first-page":"51","volume":"4","author":"CP Thacker","year":"1992","unstructured":"C. P. Thacker, D. G. Conroy, and L. C. Stewart, The Alpha demonstration unit: a high-performance multiprocessor for software and chip development, Digital Technical Journal, 4(4):51\u201365 (1992).","journal-title":"Digital Technical Journal"},{"key":"BF03356750_CR18","doi-asserted-by":"crossref","unstructured":"G. Sohi and M. Franklin, High-bandwidth data memory systems for superscalar processors, Int\u2019l. Conf. on Architectural Support for Programming Languages and Operating Systems, pp. 53\u201361 (1991).","DOI":"10.1145\/106972.106980"},{"key":"BF03356750_CR19","doi-asserted-by":"crossref","unstructured":"K. I. Farkas and N. P. Jouppi, Complexity\/performance tradeoffs with non-blocking loads, Intl. Symp. on Computer Architecture, pp. 211\u2013222 (1994).","DOI":"10.1145\/192007.192029"},{"issue":"4","key":"BF03356750_CR20","first-page":"19","volume":"4","author":"RL Sites","year":"1992","unstructured":"R. L. Sites, Alpha AXP architecture, Digital Technical Journal, 4(4): 19\u201334 (1992).","journal-title":"Digital Technical Journal"},{"issue":"4","key":"BF03356750_CR21","first-page":"100","volume":"4","author":"BR Allison","year":"1992","unstructured":"B. R. Allison and C. van Ingen, Technical description of the DEC 7000 and DEC 10000 AXP family, Digital Technical Journal, 4(4): 100\u2013110 (1992).","journal-title":"Digital Technical Journal"},{"issue":"1","key":"BF03356750_CR22","first-page":"119","volume":"7","author":"JH Edmondson","year":"1994","unstructured":"J. H. Edmondson, et al., Internal organization of the Alpha 21164, a 300-MHz 64-bit quad-issue CMOS RISC microprocessor, Digital Technical Journal, 7(1):119\u2013135 (1994).","journal-title":"Digital Technical Journal"},{"key":"BF03356750_CR23","doi-asserted-by":"crossref","unstructured":"D. H. Albonesi and I. Koren, Architecture and technology tradeoffs in the design of next-generation multiprocessor servers, IEEE Symp. on Parallel and Distributed Processing, pp. 174\u2013181 (1995).","DOI":"10.1109\/SPDP.1995.530681"}],"container-title":["International Journal of Parallel Programming"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF03356750.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/BF03356750\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BF03356750","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,8]],"date-time":"2019-09-08T21:57:07Z","timestamp":1567979827000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/BF03356750"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1996,6]]},"references-count":23,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1996,6]]}},"alternative-id":["BF03356750"],"URL":"https:\/\/doi.org\/10.1007\/bf03356750","relation":{},"ISSN":["0885-7458","1573-7640"],"issn-type":[{"value":"0885-7458","type":"print"},{"value":"1573-7640","type":"electronic"}],"subject":[],"published":{"date-parts":[[1996,6]]}}}