{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T13:21:59Z","timestamp":1725456119122},"publisher-location":"Berlin\/Heidelberg","reference-count":8,"publisher":"Springer-Verlag","isbn-type":[{"type":"print","value":"354057980X"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/bfb0020356","type":"book-chapter","created":{"date-parts":[[2005,11,23]],"date-time":"2005-11-23T08:13:09Z","timestamp":1132733589000},"page":"105-110","source":"Crossref","is-referenced-by-count":1,"title":["A distributed automatic test pattern generation system"],"prefix":"10.1007","author":[{"given":"Peter A.","family":"Krauss","sequence":"first","affiliation":[]}],"member":"297","reference":[{"key":"16_CR1","doi-asserted-by":"crossref","unstructured":"R. H. Klenke, R. D. Williams, and J. H. Aylor, \u201cParallel-Processing Techniques for Automatic Test Pattern Generation,\u201d IEEE Computer, pp. 71\u201384, 1992.","DOI":"10.1109\/2.108056"},{"key":"16_CR2","doi-asserted-by":"crossref","unstructured":"B. Ramkumar and P. Banerjee, \u201cPortable Parallel Test Generation for Sequential Circuits,\u201d in Proceedings IEEE\/ACM International Conference on Computer-Aided Design, pp. 220\u2013223, 1992.","DOI":"10.1109\/ICCAD.1992.279371"},{"key":"16_CR3","doi-asserted-by":"crossref","unstructured":"P. Agrawal, V. D. Agrawal, and J. Villoldo, \u201cSequential Circuit Test Generation on a Distributed System,\u201d in Proceedings IEEE\/ACM Design Automation Conference, pp. 107\u2013111, 1993.","DOI":"10.1145\/157485.164762"},{"key":"16_CR4","doi-asserted-by":"crossref","unstructured":"P. A. Krauss and K. J. Antreich, Application of Fault Parallelism to the Automatic Test Pattern Generation for Sequential Circuits, vol. Parallel Computer Architectures: Theory, Hardware, Software, Applications of Lecture Notes in Computer Science No. 732, pp. 234\u2013245. Springer-Verlag, 1993.","DOI":"10.1007\/978-3-662-21577-7_17"},{"key":"16_CR5","doi-asserted-by":"crossref","unstructured":"S. B. Akers and B. Krishnamurthy, \u201cTest Counting: A Tool for VLSI Testing,\u201d IEEE Design & Test of Computers, pp. 58\u201373, 1989.","DOI":"10.1109\/54.43080"},{"key":"16_CR6","doi-asserted-by":"crossref","unstructured":"S. Patil and P. Banerjee, \u201cFault Partitioning Issues in an Integrated Parallel Test Generation \/ Fault Simulation Environment,\u201d in Proceedings IEEE International Test Conference, pp. 718\u2013726, 1989.","DOI":"10.1109\/TEST.1989.82360"},{"key":"16_CR7","unstructured":"R. Butler and E. Lusk, \u201cUser's Guide to the p4 Parallel Programming System,\u201d Tech. Rep. ANL-92\/17, Argonne National Laboratory, Mathematics and Computer Science Division, 1992."},{"key":"16_CR8","doi-asserted-by":"crossref","unstructured":"F. Brglez, D. Bryan, and K. Kozminski, \u201cCombinational Profiles of Sequential Benchmark Circuits,\u201d in Proceedings IEEE International Symposium on Circuits and Systems, pp. 1929\u20131934, 1989.","DOI":"10.1109\/ISCAS.1989.100747"}],"container-title":["Lecture Notes in Computer Science","High-Performance Computing and Networking"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/www.springerlink.com\/index\/pdf\/10.1007\/BFb0020356","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,4,11]],"date-time":"2020-04-11T04:40:12Z","timestamp":1586580012000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/BFb0020356"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["354057980X"],"references-count":8,"URL":"https:\/\/doi.org\/10.1007\/bfb0020356","relation":{},"subject":[]}}