{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,30]],"date-time":"2025-12-30T23:48:44Z","timestamp":1767138524171,"version":"build-2238731810"},"publisher-location":"Berlin, Heidelberg","reference-count":16,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"value":"9783662232064","type":"print"},{"value":"9783662252093","type":"electronic"}],"license":[{"start":{"date-parts":[[1991,1,1]],"date-time":"1991-01-01T00:00:00Z","timestamp":662688000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1991]]},"DOI":"10.1007\/978-3-662-25209-3_16","type":"book-chapter","created":{"date-parts":[[2013,8,21]],"date-time":"2013-08-21T05:33:51Z","timestamp":1377063231000},"page":"219-235","source":"Crossref","is-referenced-by-count":3,"title":["Deriving Fully Efficient Systolic Arrays by Quasi-Linear Allocation Functions"],"prefix":"10.1007","author":[{"given":"Xiaoxiong","family":"Zhong","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sanjay","family":"Rajopadhye","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"16_CR1","doi-asserted-by":"crossref","unstructured":"Utpal Banerjee. Dependence Analysis for Supercompuiing. Kluwer Academic Publishers, 1988.","DOI":"10.1007\/978-1-4684-6894-6_3"},{"key":"16_CR2","doi-asserted-by":"publisher","first-page":"591","DOI":"10.1109\/ASAP.1990.145495","volume-title":"International Conference on Application Specific Array Processing","author":"J Bu","year":"1990","unstructured":"J. Bu, E. F. Deprettere, and P. Dewilde. A design methodology for fixed-size systolic arrays. In S. Y. Kung and E. Swartzlander, editors, International Conference on Application Specific Array Processing, pages 591\u2013602, Princeton, New Jersey, Sept 1990. IEEE Computer Society."},{"key":"16_CR3","doi-asserted-by":"publisher","first-page":"4","DOI":"10.1109\/ASAP.1990.145438","volume-title":"International Conference on Application Specific Array Processing","author":"P Clauss","year":"1990","unstructured":"P. Clauss, C. Mongenet, and G. R. Perrin. Calculus of space-optimal mappings of systolic algorithms on processor arrays. In S. Y. Kung and E. Swartzlander, editors, International Conference on Application Specific Array Processing, pages 4\u201318, Princeton, New Jersey, Sept 1990. IEEE Computer Society."},{"key":"16_CR4","first-page":"23","volume":"2","author":"PR Cappello","year":"1984","unstructured":"Peter R. Cappello and Kenneth Steiglitz. Unifying VLSI designs with linear transformations of space-time. Advances in Computing Research, 2: 23\u201365, 1984.","journal-title":"Advances in Computing Research"},{"key":"16_CR5","unstructured":"H. T. Kung and C. E. Leiserson. Algorithms for VLSI Processor Arrays, chapter 8.3, \u2018Introduction to VLSI Systems,\u2019 Mead, C. and Conway, L., pages 271\u2013292. Addison-Wesley, Reading, Ma, 1980."},{"issue":"3","key":"16_CR6","first-page":"563","volume":"14","author":"RM Karp","year":"1967","unstructured":"R. M. Karp, R. E. Miller, and S. Winograd. The organization of computations for uniform recurrence equations. JA CM, 14 (3): 563\u2013590, July 1967.","journal-title":"JA CM"},{"issue":"1","key":"16_CR7","first-page":"66","volume":"35","author":"GJ Li","year":"1985","unstructured":"G. J. Li and B. W. Wah. Design of optimal systolic arrays. IEEE Transactions on Computers, 35 (1): 66\u201377, 1985.","journal-title":"IEEE Transactions on Computers"},{"issue":"1","key":"16_CR8","doi-asserted-by":"publisher","first-page":"113","DOI":"10.1109\/PROC.1983.12532","volume":"71","author":"DI Moldovan","year":"1983","unstructured":"D. I. Moldovan. On the design of algorithms for VLSI systolic arrays. Proceedings of the IEEE, 71 (1): 113\u2013120, January 1983.","journal-title":"Proceedings of the IEEE"},{"key":"16_CR9","unstructured":"Patrice Quinton. The Systematic Design of Systolic Arrays,chapter 9, Automata Networks in Computer Science, pages 229\u2013260. Princeton University Press, 1987. Preliminary versions appear as IRISA Tech Reports 193 and 216, 1983."},{"key":"16_CR10","unstructured":"Sailesh Rao. Regular Iterative Algorithms and their Implementations on Processor Arrays. PhD thesis, Stanford University, Information Systems Lab., Stanford, Ca, October 1985."},{"key":"16_CR11","doi-asserted-by":"publisher","first-page":"163","DOI":"10.1016\/0167-8191(90)90105-I","volume":"14","author":"SV Rajopadhye","year":"1990","unstructured":"Sanjay V. Rajopadhye and Richard M. Fujimoto. Synthesizing systolic arrays from recurrence equations. Parallel Computing, 14: 163\u2013189, June 1990.","journal-title":"Parallel Computing"},{"key":"16_CR12","unstructured":"Sailesh Rao and Thomas Kailath. What is a systolic algorithm. In Proceedings, Highly Parallel Signal Processing Architectures,pages 34\u201348, Los Angeles, Ca, Jan 1986. SPIE."},{"key":"16_CR13","doi-asserted-by":"publisher","first-page":"2239","DOI":"10.1109\/ISCAS.1989.100823","volume-title":"International Symposium on Circuits and Systems","author":"L Thiele","year":"1989","unstructured":"Lothar Thiele. On the design of picecwise regular processor arrays. In International Symposium on Circuits and Systems, pages 2239\u20132542. IEEE CAS, IEEE Press, 1989."},{"key":"16_CR14","unstructured":"Jiwan Wong and Jean-Marc Delosme. Optimization of the processor count for systolic arrays. Technical Report YALEU-DCS-RR-697, Computer Science Dept. Yale University, May 1989."},{"key":"16_CR15","doi-asserted-by":"crossref","unstructured":"Xiaoxiong Zhong and Sanjay V. Rajopadhye. Synthesizing efficient systolic arrays. In International Conference on Acoustics, Speech and Signal Processing,pages accepted, Toronto, Canada, May 1991. IEEE.","DOI":"10.1109\/ICASSP.1991.150618"},{"key":"16_CR16","unstructured":"Xiaoxiong Zhong, Ivan M. Wong, and Sanjay V. Rajopadhye. Bounds on the solution space in systolic array design. Technical Report CIS-TR-90\u201310, University of Oregon, Computer Science Department, 120 Deschutes Hall, Eugene OR 97403\u20131202, April 1990. (submitted to Journal of VLSI Signal Processing; preliminary results reported in VLSI Signal Processing IV, San Diego CA, Nov 1990 )."}],"container-title":["Lecture Notes in Computer Science","Parle \u201991 Parallel Architectures and Languages Europe"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-662-25209-3_16","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,16]],"date-time":"2019-05-16T15:41:06Z","timestamp":1558021266000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-662-25209-3_16"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1991]]},"ISBN":["9783662232064","9783662252093"],"references-count":16,"aliases":["10.1007\/bfb0035107"],"URL":"https:\/\/doi.org\/10.1007\/978-3-662-25209-3_16","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[1991]]}}}