{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,6]],"date-time":"2025-06-06T10:25:43Z","timestamp":1749205543628},"publisher-location":"New York, NY","reference-count":21,"publisher":"Springer New York","isbn-type":[{"type":"print","value":"9780387968186"},{"type":"electronic","value":"9780387347707"}],"license":[{"start":{"date-parts":[[1988,1,1]],"date-time":"1988-01-01T00:00:00Z","timestamp":567993600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1988]]},"DOI":"10.1007\/bfb0040396","type":"book-chapter","created":{"date-parts":[[2006,8,3]],"date-time":"2006-08-03T00:03:50Z","timestamp":1154563430000},"page":"288-300","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Regular structures and testing: RCC-adders"],"prefix":"10.1007","author":[{"given":"Bernd","family":"Becker","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Uwe","family":"Sparmann","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2005,6,1]]},"reference":[{"key":"29_CR1","doi-asserted-by":"publisher","first-page":"175","DOI":"10.1145\/356914.356916","volume":"15","author":"M.S. Abadir","year":"1983","unstructured":"M.S. Abadir, H.K. Reghbati: \u2018Functional Testing of Semiconductor Random Access Memories', Computing Surveys 15, 1983, pp. 175\u2013198","journal-title":"Computing Surveys"},{"key":"29_CR2","first-page":"875","volume":"C-30","author":"J.A. Abraham","year":"1981","unstructured":"J.A. Abraham, D.D. Gajski: \u2018Design of Testable Structures Defined by Simple Loops', IEEE Tr. C-30, 1981, pp. 875\u2013883","journal-title":"IEEE Tr."},{"key":"29_CR3","doi-asserted-by":"publisher","first-page":"363","DOI":"10.1007\/BF00292108","volume":"24","author":"B. Becker","year":"1987","unstructured":"B. Becker: \u2018An Easily Testable Optimal-Time VLSI Multiplier', ACTA INF. 24, 1987, pp. 363\u2013380","journal-title":"ACTA INF."},{"key":"29_CR4","doi-asserted-by":"crossref","unstructured":"B.Becker: \u2018Efficient Testing of Optimal Time Adders', Proc. MFCS 86, Bratislava, LNCS 233, pp. 218\u2013229","DOI":"10.1007\/BFb0016245"},{"key":"29_CR5","doi-asserted-by":"crossref","unstructured":"B.Becker, R.Kolla: \u2018On the Construction of Optimal Time Adders', Proc. 5th STACS 88, Bordeaux, LNCS 294, pp. 18\u201328","DOI":"10.1007\/BFb0035828"},{"key":"29_CR6","doi-asserted-by":"publisher","first-page":"153","DOI":"10.1016\/0165-6074(87)90134-7","volume":"20","author":"B. Becker","year":"1987","unstructured":"B. Becker, H. Soukup: \u2018CMOS Stuck-Open Self-Test for an Optimal-Time VLSI-Multiplier', The Euromicro J., Microproc. and Microprog. 20, 1987 pp. 153\u2013157","journal-title":"The Euromicro J., Microproc. and Microprog."},{"key":"29_CR7","unstructured":"B.Becker, U.Sparmann: \u2018A Uniform Test Approach for RCC-Adders', T.R., 8\/1987, SFB 124, Saarbr\u00fccken 1987"},{"key":"29_CR8","first-page":"260","volume":"C-31","author":"R.P. Brent","year":"1982","unstructured":"R.P. Brent, H.T. Kung: \u2018A Regular Layout for Parallel Adders', IEEE Tr. C-31, 1982, pp. 260\u2013264","journal-title":"IEEE Tr."},{"volume-title":"Diagnosis and Reliable Design of Digital Systems","year":"1976","key":"29_CR9","unstructured":"M.A. Breuer, Ed.: \u2018Diagnosis and Reliable Design of Digital Systems', Woodland Hills, CA: Computer Science Press, 1976"},{"key":"29_CR10","first-page":"1033","volume":"CAS-28","author":"W. Daehn","year":"1981","unstructured":"W. Daehn, J. Mucha: \u2018A Hardware Approach to Self-Testing of large PLA's', IEEE Tr. CAS-28, 1981, p. 1033","journal-title":"IEEE Tr."},{"key":"29_CR11","first-page":"165","volume":"2","author":"E.B. Eichelberger","year":"1978","unstructured":"E.B. Eichelberger, T.W. Williams: \u2018A Logic Design Structure for LSI Testability', J. Design Autom. Fault-Tolerant Comput. 2, 1978, pp. 165\u2013178","journal-title":"J. Design Autom. Fault-Tolerant Comput."},{"key":"29_CR12","doi-asserted-by":"crossref","unstructured":"J.Ferguson, J.P.Shen: \u2018The Design of Two Easily-Testable VLSI Array Multipliers', Proc. 6th Symp. on Comp. Arith., 1983, Aarhus, pp. 2\u20139","DOI":"10.1109\/ARITH.1983.6158077"},{"key":"29_CR13","first-page":"1061","volume":"C-22","author":"A.D. Friedman","year":"1973","unstructured":"A.D. Friedman: \u2018Easily Testable Iterative Systems', IEEE Tr C-22, 1973, pp. 1061\u20131064","journal-title":"IEEE Tr"},{"key":"29_CR14","doi-asserted-by":"crossref","unstructured":"G.Hotz: \u2018Zur Reduktionstheorie der booleschen Algebra', Colloquium \u00fcber Schaltkreis-und Schaltwerk-Theorie, (1960) Herausgeber: Unger H., Peschel E., Birkh\u00e4user Verlag 1961","DOI":"10.1007\/978-3-0348-5770-3_3"},{"key":"29_CR15","doi-asserted-by":"crossref","unstructured":"W.H.Kautz: \u2018Testing for Faults in Cellular Logic Arrays', Proc. of 8th Symp. on Switch. Autom. Th., 1967, pp. 161\u2013174","DOI":"10.1109\/FOCS.1967.33"},{"key":"29_CR16","unstructured":"B.Koenemann, J.Mucha, G.Zwiehoff: \u2018Built-In Logic Block Observation Technique', Proc. IEEE Test Conf., 1979, pp. 37\u201341"},{"key":"29_CR17","unstructured":"R.E.Ladner, M.J.Fischer: \u2018Parallel Prefix Computation', Proc. of Intern. Conf. on Par. Proc., 1977, pp. 213\u2013223"},{"key":"29_CR18","first-page":"143","volume":"10","author":"B. Milne","year":"1985","unstructured":"B. Milne: \u2018Testability, 1985 Technology Forecast', Electronic Design, January 10, 1985, pp. 143\u2013166","journal-title":"Electronic Design"},{"key":"29_CR19","unstructured":"R.K.Montoye, J.A.Abraham: \u2018Built-in Tests for Abitrarily Structured VLSI Carry Look-Ahead Adders', IFIP 1983, pp. 361\u2013371"},{"key":"29_CR20","first-page":"226","volume":"9","author":"J. Sklansky","year":"1960","unstructured":"J. Sklansky: \u2018Conditional-sum Addition Logic', IRE-EC 9, 1960, pp. 226\u2013231","journal-title":"IRE-EC"},{"key":"29_CR21","first-page":"845","volume":"C-28","author":"J.E. Smith","year":"1979","unstructured":"J.E. Smith: \u2018Detection of Faults in PLA's', IEEE Tr. C-28, 1979, p. 845","journal-title":"IEEE Tr."}],"container-title":["Lecture Notes in Computer Science","VLSI Algorithms and Architectures"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BFb0040396","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,1,8]],"date-time":"2020-01-08T19:44:18Z","timestamp":1578512658000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/BFb0040396"}},"subtitle":["Extended abstract"],"short-title":[],"issued":{"date-parts":[[1988]]},"ISBN":["9780387968186","9780387347707"],"references-count":21,"URL":"https:\/\/doi.org\/10.1007\/bfb0040396","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[1988]]},"assertion":[{"value":"1 June 2005","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}