{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,25]],"date-time":"2025-03-25T16:16:39Z","timestamp":1742919399504,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":12,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540649489"},{"type":"electronic","value":"9783540680666"}],"license":[{"start":{"date-parts":[[1998,1,1]],"date-time":"1998-01-01T00:00:00Z","timestamp":883612800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[1998,1,1]],"date-time":"1998-01-01T00:00:00Z","timestamp":883612800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1998]]},"DOI":"10.1007\/bfb0055240","type":"book-chapter","created":{"date-parts":[[2006,7,27]],"date-time":"2006-07-27T08:11:44Z","timestamp":1153987904000},"page":"129-138","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Fast floorplanning for FPGAs"],"prefix":"10.1007","author":[{"given":"John M.","family":"Emmert","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Akash","family":"Randhar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dinesh","family":"Bhatia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2006,5,27]]},"reference":[{"key":"14_CR1","doi-asserted-by":"crossref","unstructured":"C. Fiduccia and R. Mattheyses, \u201cA Linear time Heuristic for Improving Network Partitions\u201d, Proc. of DAC, pp.175\u2013181, June 1982.","DOI":"10.1145\/800263.809204"},{"key":"14_CR2","unstructured":"M. Breuer, \u201cA class of min-cut placement algorithms\u201d, Proc. of DAC, pp. 284\u2013290, 1980."},{"key":"14_CR3","doi-asserted-by":"crossref","unstructured":"A. E. Dunlop and B. W. Kernighan, \u201cA Procedure for Placement of Standard-Cell VLSI Circuits\u201d, IEEE Transactions on Computer-Aided Design, pp. 92\u201398, January 1985.","DOI":"10.1109\/TCAD.1985.1270101"},{"key":"14_CR4","unstructured":"J. M. Emmert and D. K. Bhatia, \u201cFast Placement Using TABU Search for Total Wire Length Minimization\u201d, University of Cincinnati, ECECS Technical Report, 1998."},{"key":"14_CR5","unstructured":"Jianzhong Shi, Akash Randhar and Dinesh Bhatia \u201cMacro block based FPGA Floorplanning\u201d Proc. of Intl. Conf. on VLSI Design, January 1997."},{"key":"14_CR6","doi-asserted-by":"crossref","unstructured":"J. Shi and D. Bhatia, \u201cPerformance Driven Floorplanning for FPGA Based Designs\u201d Proc. of ACM Symposium on Field Programmable Gate Arrays, February 1997.","DOI":"10.1145\/258305.258321"},{"key":"14_CR7","doi-asserted-by":"crossref","unstructured":"A. Mathur and C.L. Liu, \u201cCompression-Relaxation: A New Approach to Timing Driven Placement for Regular Architectures\u201d IEEE Transactions on CAD of Integrated Circuits and Systems, pp. 597\u2013608, June 1997.","DOI":"10.1109\/43.640618"},{"key":"14_CR8","unstructured":"A. Randhar, \u201cMacro Based Floorplanning for FPGAs\u201d Thesis: University of Cincinnati, December 1997."},{"key":"14_CR9","doi-asserted-by":"crossref","unstructured":"C. Sechen \u201cChip Planning, Placement, and Global Routing of Macro\/Custom Cell integrated Circuits Using Simulated Annealing\u201d in Proc. of DAC, pp. 73\u201380, June 1988.","DOI":"10.1007\/978-1-4613-1697-8_4"},{"key":"14_CR10","unstructured":"A. Subramaniam and D. Bhatia \u201cTiming Driven Placement for Logic Cell Arrays\u201d University of Cincinnati, ECECS Technical Report, 1994."},{"key":"14_CR11","doi-asserted-by":"crossref","unstructured":"D.F. Wong and C.L. Liu \u201cA new method for floorplan design\u201d Proc. of DAC, pp. 101\u2013107, 1986.","DOI":"10.1109\/DAC.1986.1586075"},{"key":"14_CR12","unstructured":"www.xilinx.com."}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications From FPGAs to Computing Paradigm"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/BFb0055240","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,7]],"date-time":"2022-07-07T12:32:48Z","timestamp":1657197168000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/BFb0055240"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998]]},"ISBN":["9783540649489","9783540680666"],"references-count":12,"URL":"https:\/\/doi.org\/10.1007\/bfb0055240","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[1998]]},"assertion":[{"value":"27 May 2006","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}