{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T03:52:44Z","timestamp":1743047564357,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":10,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540649489"},{"type":"electronic","value":"9783540680666"}],"license":[{"start":{"date-parts":[[1998,1,1]],"date-time":"1998-01-01T00:00:00Z","timestamp":883612800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[1998,1,1]],"date-time":"1998-01-01T00:00:00Z","timestamp":883612800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1998]]},"DOI":"10.1007\/bfb0055256","type":"book-chapter","created":{"date-parts":[[2006,7,27]],"date-time":"2006-07-27T08:11:44Z","timestamp":1153987904000},"page":"288-297","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["High-level synthesis for dynamically reconfigurable hardware\/software systems"],"prefix":"10.1007","author":[{"given":"Rainer","family":"Kress","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreas","family":"Pyttel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2006,5,27]]},"reference":[{"key":"30_CR1","doi-asserted-by":"crossref","unstructured":"J. Fleischmann, K. Buchenrieder, R. Kress: A Hardware\/Software Prototyping Environment for Dynamically Reconfigurable Embedded Systems; 6th International Workshop on Hardware\/Software Codesign, CODES\/CASHE'98, Seattle, March 1998","DOI":"10.1145\/278241.278310"},{"key":"30_CR2","unstructured":"M. Kaul, R. Vemuri: Optimal Temporal Partitioning for Reconfigurable Architectures; Design Automation and Test Conference in Europe, DATE'98, Paris, Feb. 1998"},{"key":"30_CR3","doi-asserted-by":"crossref","unstructured":"Y.-L. Lin: Recent Developments in High-Level Synthesis; ACM Transactions on Design Automation of Electronic Systems, vol. 2, no. 1, Jan. 1997","DOI":"10.1145\/250243.250245"},{"key":"30_CR4","volume-title":"Configuration Controller Synthesis for Dynamically Reconfigurable Systems","author":"P. Lysaght","year":"1998","unstructured":"P. Lysaght, G. McGregor, J. Stockwood: Configuration Controller Synthesis for Dynamically Reconfigurable Systems; IEE Colloquium on Hardware\/Software Cosynthesis for Reconfigurable Systems, HP Labs., Bristol, UK, Feb. 1998"},{"key":"30_CR5","doi-asserted-by":"crossref","unstructured":"W. Luk, N. Shirazi, S. R. Guo, P. Y. K. Cheung: Pipeline Morphing and Virtual Pipelines; in W. Luk, P. Y. K. Cheung, M. Glesner (Eds.):Field-Programmable Logic and Applications, Lecture Notes in Computer Science 1304, Sept. 1997","DOI":"10.1007\/3-540-63465-7_216"},{"key":"30_CR6","unstructured":"A. Pyttel, A. Sedlmeier: HW\/SW Systems Prototyping with Statically and Dynamically Reconfigurable FPGAs; Design Automation and Test Conference in Europe, DATE'98, Designer Track, Paris, Feb. 1998"},{"key":"30_CR7","unstructured":"M. Vasilko: Bournemouth University Page of Dynamically Reconfigurable Hardware; http:\/\/dec.bournemouth.ac.uk\/dec_ind\/decind6\/drhw_page.html, Jan. 1997"},{"key":"30_CR8","doi-asserted-by":"crossref","unstructured":"M. Vasilko, D. Ait-Boudadoud: Architectural Synthesis Techniques for Dynamically Reconfigurable Logic; in Hartenstein, Glesner (Eds.): Field-Programmable Logic: Smart Applications, New Paradigms and Compilers, Lecture Notes in Computer Science 1142, Sept. 1996","DOI":"10.1007\/3-540-61730-2_31"},{"key":"30_CR9","volume-title":"The Programmable Logic Data Book","author":"N. N","year":"1996","unstructured":"N. N.: The Programmable Logic Data Book; Xilinx Inc., San Jos\u00e9, CA, 1996"},{"key":"30_CR10","volume-title":"Xilinx Application Note XAPP 082","author":"N. N","year":"1997","unstructured":"N. N.: A Fast Constant Coefficient Multiplier for the XC6200; Xilinx Application Note XAPP 082, Xilinx Inc., San Jos\u00e9, CA, Aug. 1997"}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications From FPGAs to Computing Paradigm"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/BFb0055256","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,7]],"date-time":"2022-07-07T12:33:53Z","timestamp":1657197233000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/BFb0055256"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998]]},"ISBN":["9783540649489","9783540680666"],"references-count":10,"URL":"https:\/\/doi.org\/10.1007\/bfb0055256","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[1998]]},"assertion":[{"value":"27 May 2006","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}