{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T18:28:15Z","timestamp":1725474495821},"publisher-location":"Berlin, Heidelberg","reference-count":4,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540658313"},{"type":"electronic","value":"9783540489320"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1999]]},"DOI":"10.1007\/bfb0097956","type":"book-chapter","created":{"date-parts":[[2006,11,24]],"date-time":"2006-11-24T09:45:17Z","timestamp":1164361517000},"page":"700-702","source":"Crossref","is-referenced-by-count":0,"title":["An on-line arithmetic-based reconfigurable neuroprocessor"],"prefix":"10.1007","author":[{"given":"Jean-Luc","family":"Beuchat","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eduardo","family":"Sanchez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2006,10,28]]},"reference":[{"key":"74_CR1","doi-asserted-by":"crossref","unstructured":"J.G. Eldredge and B.L. Hutchings. Density Enhancement of a Neural Network Using FPGAs and Run-Time Reconfiguration. In Duncan A. Buell and Kenneth L. Pocek, editors, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pages 180\u2013188. IEEE Computer Society Press, 1994.","DOI":"10.1109\/FPGA.1994.315611"},{"key":"74_CR2","doi-asserted-by":"crossref","unstructured":"Jean-Luc Beuchat and Eduardo Sanchez. A Reconfigurable Neuroprocessor with On-chip Pruning. In L. Niklasson, M. Bod\u00e9n, and T. Ziemke, editors, ICANN 98, Perspectives in Neural Computing, pages 1159\u20131164. Springer, 1998.","DOI":"10.1007\/978-1-4471-1599-1_182"},{"key":"74_CR3","doi-asserted-by":"crossref","unstructured":"Kishor S. Trivedi and Milos D. Ercegovac. On-line Algorithms for Division and Multiplication. IEEE Transaction on Computers, C-26(7), July 1977.","DOI":"10.1109\/TC.1977.1674901"},{"key":"74_CR4","doi-asserted-by":"crossref","unstructured":"Algirdas Avizienis. Signed-Digit Number Representations for Fast Parallel Arithmetic. IRE Transactions on Electronic Computers, 10, 1961.","DOI":"10.1109\/TEC.1961.5219227"}],"container-title":["Lecture Notes in Computer Science","Parallel and Distributed Processing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/BFb0097956","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,4,22]],"date-time":"2019-04-22T10:59:28Z","timestamp":1555930768000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/BFb0097956"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999]]},"ISBN":["9783540658313","9783540489320"],"references-count":4,"URL":"https:\/\/doi.org\/10.1007\/bfb0097956","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[1999]]}}}