{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,4]],"date-time":"2024-07-04T13:13:15Z","timestamp":1720098795447},"reference-count":34,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2013,10,11]],"date-time":"2013-10-11T00:00:00Z","timestamp":1381449600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2014,3]]},"DOI":"10.1007\/s00034-013-9669-1","type":"journal-article","created":{"date-parts":[[2013,10,11]],"date-time":"2013-10-11T17:30:20Z","timestamp":1381512620000},"page":"863-884","source":"Crossref","is-referenced-by-count":4,"title":["DA-Based Efficient Testable FIR Filter Implementation on FPGA Using Reversible Logic"],"prefix":"10.1007","volume":"33","author":[{"given":"Amita","family":"Nandal","sequence":"first","affiliation":[]},{"given":"T.","family":"Vigneswaran","sequence":"additional","affiliation":[]},{"given":"Ashwani K.","family":"Rana","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2013,10,11]]},"reference":[{"key":"9669_CR1","doi-asserted-by":"crossref","first-page":"50","DOI":"10.1109\/DSD.2003.1231899","volume-title":"Proc. of EuroMicro Symposium on Digital System Design","author":"H.M.H. Babu","year":"2003","unstructured":"H.M.H. Babu, M.R. Islam, A.R. Chowdhury, S.M.A. Chowdhury, Reversible logic synthesis for minimization of full adder circuit, in Proc. of EuroMicro Symposium on Digital System Design, Sept (2003), pp. 50\u201354"},{"key":"9669_CR2","doi-asserted-by":"crossref","first-page":"757","DOI":"10.1109\/ICVD.2004.1261020","volume-title":"Proc. of 17th International Conference on VLSI Design","author":"H.M.H. Babu","year":"2004","unstructured":"H.M.H. Babu, M.R. Islam, S.M.A. Chowdhury, A.R. Chowdhury, Synthesis of full adder circuit using reversible logic, in Proc. of 17th International Conference on VLSI Design, Jan (2004), pp. 757\u2013760"},{"key":"9669_CR3","volume-title":"Digital Signal Processing with FPGA","author":"U.M. Baese","year":"2006","unstructured":"U.M. Baese, Digital Signal Processing with FPGA (Tsinghua University Press, Beijing, 2006), 50"},{"key":"9669_CR4","doi-asserted-by":"crossref","first-page":"525","DOI":"10.1147\/rd.176.0525","volume":"17","author":"C.H. Bennett","year":"1973","unstructured":"C.H. Bennett, Logical reversibility of computation. IBM J. Res. Dev. 17, 525\u2013532 (1973)","journal-title":"IBM J. Res. Dev."},{"key":"9669_CR5","first-page":"444","volume-title":"Proc. of International Conference on Dependable Systems and Networks","author":"P.O. Boykin","year":"2005","unstructured":"P.O. Boykin, V.P. Roychowdhury, Reversible fault-tolerant logic, in Proc. of International Conference on Dependable Systems and Networks, June (2005), pp. 444\u2013453"},{"key":"9669_CR6","doi-asserted-by":"crossref","first-page":"235","DOI":"10.1007\/BF00925468","volume":"2","author":"W.P. Burleson","year":"1991","unstructured":"W.P. Burleson, L.L. Scharf, A VLSI design method for distributed arithmetic. VLSI Signal Process. 2, 235\u2013252 (1991)","journal-title":"VLSI Signal Process."},{"issue":"14","key":"9669_CR7","first-page":"9","volume":"59","author":"S. Buyya","year":"2012","unstructured":"S. Buyya, C.J. Bhavi, Quantum cost realization of reversible barrel shifter. Int. J. Comput. Appl. 59(14), 9\u201311 (2012)","journal-title":"Int. J. Comput. Appl."},{"key":"9669_CR8","first-page":"668","volume-title":"Proc. IEEE Int. Symp. Circuits Syst.","author":"H.Q. Cao","year":"1996","unstructured":"H.Q. Cao, W. Li, VLSI implementation of vector quantization using distributed arithmetic, in Proc. IEEE Int. Symp. Circuits Syst., May (1996), pp. 668\u2013671"},{"issue":"6","key":"9669_CR9","doi-asserted-by":"crossref","first-page":"163","DOI":"10.1109\/97.923040","volume":"8","author":"S.C. Chan","year":"2001","unstructured":"S.C. Chan, W. Liu, K.L. Ho, Multiplierless perfect reconstruction modulated filter banks with sum-of-powers-of-two coefficients. IEEE Signal Process. Lett. 8(6), 163\u2013166 (2001)","journal-title":"IEEE Signal Process. Lett."},{"issue":"4","key":"9669_CR10","doi-asserted-by":"crossref","first-page":"709","DOI":"10.1109\/TCSI.2004.823659","volume":"51","author":"T. Conway","year":"2004","unstructured":"T. Conway, Galois field arithmetic over GF(pm) for high-speed\/low-power error-control applications. IEEE Trans. Circuits Syst. 51(4), 709\u2013717 (2004)","journal-title":"IEEE Trans. Circuits Syst."},{"key":"9669_CR11","unstructured":"A. Croisier, D.J. Esteban, M.E. Levilion, V. Rizo, Digital filter for PCM encoded signals. U.S. Patent No. 3,777,130 (1973)"},{"issue":"8","key":"9669_CR12","doi-asserted-by":"crossref","first-page":"663","DOI":"10.1109\/LSP.2004.831725","volume":"11","author":"G. Dempster","year":"2004","unstructured":"G. Dempster, M.D. Macleod, Generation of signed-digit representations for integer multiplication. IEEE Signal Process. Lett. 11(8), 663\u2013665 (2004)","journal-title":"IEEE Signal Process. Lett."},{"issue":"7","key":"9669_CR13","doi-asserted-by":"crossref","first-page":"490","DOI":"10.1109\/82.298385","volume":"41","author":"J.B. Evans","year":"2002","unstructured":"J.B. Evans, Efficient FIR filter architectures suitable for FPGA implementation. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. 41(7), 490\u2013493 (2002)","journal-title":"IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process."},{"key":"9669_CR14","unstructured":"P. Gigliotti, Implementing barrel shifters using multipliers. XAPP195. 1 (2004)"},{"issue":"1","key":"9669_CR15","first-page":"974","volume":"3","author":"M. Haghparast","year":"2008","unstructured":"M. Haghparast, S.J. Jassbi, K. Navi, O. Hashemipour, Design of a novel reversible multiplier circuit using HNG gate in nanotechnology. World Appl. Sci. J. 3(1), 974\u2013978 (2008)","journal-title":"World Appl. Sci. J."},{"key":"9669_CR16","first-page":"261","volume-title":"Proc. IWLS","author":"A. Khlopotine","year":"2002","unstructured":"A. Khlopotine, M. Perkowski, P. Kerntopf, Reversible logic synthesis by gate composition, in Proc. IWLS, June (2002), pp. 261\u2013266"},{"key":"9669_CR17","doi-asserted-by":"crossref","first-page":"577","DOI":"10.1109\/82.769806","volume":"46","author":"Y.C. Lim","year":"1999","unstructured":"Y.C. Lim, R. Yang, D. Li, J. Song, Signed power-of-two term allocation scheme for the design of digital filters. IEEE Trans. Circuits Syst. II 46, 577\u2013584 (1999)","journal-title":"IEEE Trans. Circuits Syst. II"},{"issue":"7","key":"9669_CR18","doi-asserted-by":"crossref","first-page":"3009","DOI":"10.1109\/TSP.2007.914926","volume":"56","author":"P.K. Meher","year":"2008","unstructured":"P.K. Meher, S. Chandrasekaran, A. Amira, FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic. IEEE Trans. Signal Process. 56(7), 3009\u20133017 (2008)","journal-title":"IEEE Trans. Signal Process."},{"key":"9669_CR19","first-page":"74","volume-title":"Proc. IEEE Int. Conf. TENCON\u201989","author":"S.N. Merchant","year":"1989","unstructured":"S.N. Merchant, B.V. Rao, Distributed arithmetic architecture for image coding, in Proc. IEEE Int. Conf. TENCON\u201989, Nov (1989), pp. 74\u201377"},{"key":"9669_CR20","volume-title":"Proc. of International Symposium on System on Chip","author":"P. Metzgen","year":"2004","unstructured":"P. Metzgen, Optimizing a high performance 32-bit processor for programmable logic, in Proc. of International Symposium on System on Chip, Nov (2004)"},{"issue":"4","key":"9669_CR21","doi-asserted-by":"crossref","first-page":"921","DOI":"10.1109\/TSP.2012.2226453","volume":"61","author":"B.K. Mohanty","year":"2013","unstructured":"B.K. Mohanty, P.K. Meher, A high-performance energy-efficient architecture for FIR adaptive filter based on new distributed arithmetic formulation of block LMS algorithm. IEEE Trans. Signal Process. 61(4), 921\u2013930 (2013)","journal-title":"IEEE Trans. Signal Process."},{"key":"9669_CR22","first-page":"474","volume-title":"International Conference on Signal Processing Systems","author":"N.M. Nayeem","year":"2009","unstructured":"N.M. Nayeem, M.A. Hossain, L. Jamal, H.M.H. Babu, Efficient design of shift registers using reversible logic, in International Conference on Signal Processing Systems, Singapore, May (2009), pp. 474\u2013478"},{"key":"9669_CR23","unstructured":"B. New, A distributed arithmetic approach to designing scalable DSP chips. EDN, 107\u2013114 (1995)"},{"key":"9669_CR24","doi-asserted-by":"crossref","first-page":"231","DOI":"10.1016\/S0065-2458(08)60610-5","volume":"1","author":"G.W. Reitweisner","year":"1960","unstructured":"G.W. Reitweisner, Binary arithmetic. Adv. Comput. 1, 231\u2013308 (1960)","journal-title":"Adv. Comput."},{"issue":"7","key":"9669_CR25","doi-asserted-by":"crossref","first-page":"1044","DOI":"10.1109\/31.31347","volume":"36","author":"H. Samueli","year":"1989","unstructured":"H. Samueli, An improved search algorithm for the design of multiplierless FIR filters with powers-of-two coefficients. IEEE Trans. Circuits Syst. 36(7), 1044\u20131047 (1989)","journal-title":"IEEE Trans. Circuits Syst."},{"key":"9669_CR26","volume-title":"Proc. of IEEE Int. Symp. on Circuits and Systems","author":"C.L. Su","year":"1997","unstructured":"C.L. Su, Y.T. Hwang, C.W. Jen, A novel recursive digital filter based on signed digit distributed arithmetic, in Proc. of IEEE Int. Symp. on Circuits and Systems, 2 (1997)"},{"issue":"9","key":"9669_CR27","doi-asserted-by":"crossref","first-page":"1468","DOI":"10.1109\/TMI.2009.2017740","volume":"28","author":"G.J. Tearney","year":"2009","unstructured":"G.J. Tearney, B.E. Bouma, Real-time FPGA processing for high-speed optical frequency domain imaging. IEEE Trans. Med. Imaging 28(9), 1468\u20131472 (2009)","journal-title":"IEEE Trans. Med. Imaging"},{"issue":"4","key":"9669_CR28","doi-asserted-by":"crossref","first-page":"14","DOI":"10.1145\/1877745.1877748","volume":"6","author":"H. Thapliyal","year":"2010","unstructured":"H. Thapliyal, N. Ranganathan, Design of reversible sequential circuits optimizing quantum cost, delay and garbage outputs. ACM J. Emerg. Technol. Comput. Syst. 6(4), 14 (2010)","journal-title":"ACM J. Emerg. Technol. Comput. Syst."},{"key":"9669_CR29","first-page":"100","volume-title":"IEEE Int. Conf. Computer Systems and Applications","author":"H. Thapliyal","year":"2006","unstructured":"H. Thapliyal, M.B. Srinivas, Novel reversible multiplier architecture using reversible TSG gate, in IEEE Int. Conf. Computer Systems and Applications, Mar (2006), pp. 100\u2013103"},{"issue":"2","key":"9669_CR30","doi-asserted-by":"crossref","first-page":"217","DOI":"10.1109\/4.127346","volume":"27","author":"G.M. Tharakan","year":"1992","unstructured":"G.M. Tharakan, S.M. Kang, A new design of a fast barrel switch network. IEEE J. Solid-State Circuits 27(2), 217\u2013221 (1992)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"9669_CR31","first-page":"1","volume-title":"9th International Conference on Electrical Engineering\/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON)","author":"A. Trakultritrung","year":"2012","unstructured":"A. Trakultritrung, E. Thanangchusin, S. Chivapreecha, Distributed arithmetic LMS adaptive filter implementation without look-up table, in 9th International Conference on Electrical Engineering\/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), July (2012), pp. 1\u20134"},{"key":"9669_CR32","first-page":"324","volume-title":"Proc. Symposium on Defect and Fault Tolerance","author":"D.P. Vasudevan","year":"2004","unstructured":"D.P. Vasudevan, P.K. Lala, J.P. Parkerson, Online testable reversible logic circuit design using NAND blocks, in Proc. Symposium on Defect and Fault Tolerance, Oct (2004), pp. 324\u2013331"},{"issue":"2","key":"9669_CR33","doi-asserted-by":"crossref","first-page":"406","DOI":"10.1109\/TIM.2006.870319","volume":"55","author":"D.P. Vasudevan","year":"2006","unstructured":"D.P. Vasudevan, P.K. Lala, J.P. Parkerson, Reversible-logic design with online testability. IEEE Trans. Instrum. Meas. 55(2), 406\u2013414 (2006)","journal-title":"IEEE Trans. Instrum. Meas."},{"issue":"3","key":"9669_CR34","doi-asserted-by":"crossref","first-page":"4","DOI":"10.1109\/53.29648","volume":"6","author":"S.A. White","year":"1989","unstructured":"S.A. White, Applications of distributed arithmetic to digital signal processing. A tutorial review. IEEE ASSP Mag. 6(3), 4\u201319 (1989)","journal-title":"IEEE ASSP Mag."}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-013-9669-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s00034-013-9669-1\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-013-9669-1","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,22]],"date-time":"2019-05-22T15:01:41Z","timestamp":1558537301000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s00034-013-9669-1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10,11]]},"references-count":34,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2014,3]]}},"alternative-id":["9669"],"URL":"https:\/\/doi.org\/10.1007\/s00034-013-9669-1","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"value":"0278-081X","type":"print"},{"value":"1531-5878","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,10,11]]}}}