{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,28]],"date-time":"2025-08-28T12:21:32Z","timestamp":1756383692523},"reference-count":24,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2013,10,31]],"date-time":"2013-10-31T00:00:00Z","timestamp":1383177600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2014,4]]},"DOI":"10.1007\/s00034-013-9688-y","type":"journal-article","created":{"date-parts":[[2013,10,31]],"date-time":"2013-10-31T00:33:17Z","timestamp":1383179597000},"page":"1019-1034","source":"Crossref","is-referenced-by-count":2,"title":["Designing Dynamic Carry Skip Adders: Analysis and Comparison"],"prefix":"10.1007","volume":"33","author":[{"given":"Raffaele","family":"De Rose","sequence":"first","affiliation":[]},{"given":"Marco","family":"Lanuzza","sequence":"additional","affiliation":[]},{"given":"Fabio","family":"Frustaci","sequence":"additional","affiliation":[]},{"given":"Sohan","family":"Purohit","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2013,10,31]]},"reference":[{"issue":"12","key":"9688_CR1","doi-asserted-by":"crossref","first-page":"1322","DOI":"10.1109\/TVLSI.2006.887809","volume":"14","author":"M. Alioto","year":"2006","unstructured":"M. Alioto, G. Palumbo, Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 14(12), 1322\u20131335 (2006)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"23","key":"9688_CR2","doi-asserted-by":"crossref","first-page":"1258","DOI":"10.1049\/el:20071613","volume":"43","author":"A.A. Amin","year":"2007","unstructured":"A.A. Amin, Area-efficient high-speed carry chain. Electron. Lett. 43(23), 1258\u20131260 (2007)","journal-title":"Electron. Lett."},{"key":"9688_CR3","volume-title":"Design of High Performance Microprocessor Circuits","author":"A. Chandrakasan","year":"2001","unstructured":"A. Chandrakasan, W. Bowhill, F. Fox, Design of High Performance Microprocessor Circuits (IEEE Press, New York, 2001)"},{"key":"9688_CR4","first-page":"124","volume-title":"Proc. of IEEE 22nd International Conference on Microelectronics","author":"R. Rose De","year":"2010","unstructured":"R. De Rose, M. Lanuzza, F. Frustaci, Design and Evaluation of High-Speed Energy-Aware Carry Skip Adders, in Proc. of IEEE 22nd International Conference on Microelectronics (2010), pp. 124\u2013127"},{"key":"9688_CR5","first-page":"84","volume-title":"Proc. of ISCAS 2001","author":"H. Eriksson","year":"2001","unstructured":"H. Eriksson, P. Larsson-Edefors, A. Alvandopour, A 2.8\u00a0ns 30\u00a0mW\/MHz area-efficient 32-b Manchester carry-bypass adder, in Proc. of ISCAS 2001 (2001), pp. 84\u201387"},{"issue":"6","key":"9688_CR6","doi-asserted-by":"crossref","first-page":"303","DOI":"10.1049\/iet-cds.2009.0099","volume":"3","author":"F. Frustaci","year":"2009","unstructured":"F. Frustaci, M. Lanuzza, P. Zicari, S. Perri, P. Corsonello, Low-Power Split-Path Data-Driven Dynamic Logic (SPD3L). IET Circuits Devices Syst. 3(6), 303\u2013312 (2009)","journal-title":"IET Circuits Devices Syst."},{"issue":"2","key":"9688_CR7","doi-asserted-by":"crossref","first-page":"172","DOI":"10.1109\/TCSII.2008.2010187","volume":"56","author":"F. Frustaci","year":"2009","unstructured":"F. Frustaci, M. Lanuzza, P. Zicari, S. Perri, P. Corsonello, Designing High Speed Adders in Power-Constrained Environments. IEEE Trans. Circuits Syst. II 56(2), 172\u2013176 (2009)","journal-title":"IEEE Trans. Circuits Syst. II"},{"issue":"8","key":"9688_CR8","doi-asserted-by":"crossref","first-page":"138","DOI":"10.1109\/92.831434","volume":"2","author":"S. Hauck","year":"2000","unstructured":"S. Hauck, M. Hosler, T.W. Fry, High-performance carry chains for FPGA\u2019s. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2(8), 138\u2013147 (2000)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"9688_CR9","first-page":"92","volume-title":"Proc. of IEEE Int. Solid-State Circuits Conf.","author":"P. Hofstee","year":"2000","unstructured":"P. Hofstee et al., 1 GHz single-issue 64b PowerPC processor, in Proc. of IEEE Int. Solid-State Circuits Conf. (2000), pp. 92\u201393"},{"issue":"5","key":"9688_CR10","doi-asserted-by":"crossref","first-page":"807","DOI":"10.1109\/4.668997","volume":"33","author":"H. Kawaguchi","year":"1998","unstructured":"H. Kawaguchi, T. Sakurai, A reduced clock-swing flip-flop (RCSFF) for 63\u00a0% power reduction. IEEE J. Solid-State Circuits 33(5), 807\u2013811 (1998)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"9688_CR11","doi-asserted-by":"crossref","first-page":"1679","DOI":"10.1016\/j.microrel.2012.03.024","volume":"52","author":"M. Lanuzza","year":"2012","unstructured":"M. Lanuzza, R. De Rose, F. Frustaci, S. Perri, P. Corsonello, Comparative analysis of yield optimized pulsed flip-flops. Microelectron. Reliab. 52, 1679\u20131689 (2012)","journal-title":"Microelectron. Reliab."},{"issue":"45","key":"9688_CR12","doi-asserted-by":"crossref","first-page":"1191","DOI":"10.1109\/81.735441","volume":"11","author":"J.H. Lou","year":"1998","unstructured":"J.H. Lou, J.B. Kuo, A 1.5 V bootstrapped pass-transistor-based Manchester carry chain circuit suitable for implementing low-voltage carry look-ahead adders. IEEE Trans. Circuits Syst. I, Fundam. Theory Appl. 11(45), 1191\u20131194 (1998)","journal-title":"IEEE Trans. Circuits Syst. I, Fundam. Theory Appl."},{"key":"9688_CR13","volume-title":"Computer Arithmetic: Algorithms and Hardware Designs","author":"B. Parhami","year":"2000","unstructured":"B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs (Oxford University Press, London, 2000)"},{"issue":"3","key":"9688_CR14","doi-asserted-by":"crossref","first-page":"326","DOI":"10.1166\/jolpe.2009.1033","volume":"5","author":"S. Purhoit","year":"2009","unstructured":"S. Purhoit, M. Lanuzza, S. Perri, P. Corsonello, M. Margala, Design and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems. J. Low Power Electron. 5(3), 326\u2013338 (2009)","journal-title":"J. Low Power Electron."},{"key":"9688_CR15","doi-asserted-by":"crossref","first-page":"493","DOI":"10.1145\/1531542.1531654","volume-title":"Proc. of the ACM Great Lakes Symposium on VLSI, GLSVLSI","author":"S. Purhoit","year":"2009","unstructured":"S. Purhoit, M. Lanuzza, M. Margala, New Performance\/Power\/Area Efficient Reliable Full Adder Design, in Proc. of the ACM Great Lakes Symposium on VLSI, GLSVLSI (2009), pp. 493\u2013498"},{"issue":"4","key":"9688_CR16","doi-asserted-by":"crossref","first-page":"469","DOI":"10.1166\/jolpe.2010.1096","volume":"6","author":"S. Purhoit","year":"2010","unstructured":"S. Purhoit, M. Lanuzza, M. Margala, Design Space Exploration of Split-Path Data Driven Dynamic Full Adder. J. Low Power Electron. 6(4), 469\u2013481 (2010)","journal-title":"J. Low Power Electron."},{"key":"9688_CR17","volume-title":"Digital Integrated Circuits","author":"M. Rabaey","year":"2002","unstructured":"M. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits (Prentice-Hall, New York, 2002)"},{"key":"9688_CR18","first-page":"752","volume-title":"Proc. of IEEE International Symposium on Circuits and Systems, ISCAS 2000","author":"R. Rafati","year":"2000","unstructured":"R. Rafati, S.M. Fakhraie, K.C. Smith, Lower-Power Data-Driven Dynamic Logic (D3L), in Proc. of IEEE International Symposium on Circuits and Systems, ISCAS 2000 (2000), pp. 752\u2013755"},{"key":"9688_CR19","doi-asserted-by":"crossref","first-page":"584","DOI":"10.1109\/4.52187","volume":"25","author":"T. Sakurai","year":"1990","unstructured":"T. Sakurai, A.R. Newton, Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE J. Solid-State Circuits 25, 584\u2013594 (1990)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"9688_CR20","doi-asserted-by":"crossref","first-page":"380","DOI":"10.1109\/GLSV.1999.757461","volume-title":"Proc. of the 9th Great Lakes Symposium on VLSI","author":"R. Shalem","year":"1999","unstructured":"R. Shalem, E. John, L.K. John, A novel low power energy recovery full adder cell, in Proc. of the 9th Great Lakes Symposium on VLSI (1999), pp. 380\u2013383"},{"key":"9688_CR21","volume-title":"Logical Effort","author":"I. Sutherland","year":"1999","unstructured":"I. Sutherland, R. Sproull, D. Harris, Logical Effort (Morgan Kaufmann, San Mateo, 1999)"},{"key":"9688_CR22","volume-title":"Principles of CMOS VLSI Design","author":"N. Weste","year":"1993","unstructured":"N. Weste, K. Eshraghian, Principles of CMOS VLSI Design (Addison-Wesley, Reading, 1993)"},{"key":"9688_CR23","first-page":"201","volume-title":"Proc. of VLSI Design","author":"S.S. Yoon","year":"2004","unstructured":"S.S. Yoon, S.R. Yoon, S.W. Kim, C. Kim, Charge-Sharing-Problem Reduced Split-Path Domino Logic, in Proc. of VLSI Design (2004), pp. 201\u2013205"},{"key":"9688_CR24","first-page":"404","volume-title":"Proc. of PATMOS","author":"R. Zlatanovic","year":"2005","unstructured":"R. Zlatanovic, B. Nikolic, Power-Performance Optimization for Custom Digital Circuits, in Proc. of PATMOS (2005), pp. 404\u2013414"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-013-9688-y.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s00034-013-9688-y\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-013-9688-y","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,22]],"date-time":"2019-05-22T15:01:42Z","timestamp":1558537302000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s00034-013-9688-y"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10,31]]},"references-count":24,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2014,4]]}},"alternative-id":["9688"],"URL":"https:\/\/doi.org\/10.1007\/s00034-013-9688-y","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"type":"print","value":"0278-081X"},{"type":"electronic","value":"1531-5878"}],"subject":[],"published":{"date-parts":[[2013,10,31]]}}}