{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T15:22:55Z","timestamp":1761578575675,"version":"3.40.4"},"reference-count":19,"publisher":"Springer Science and Business Media LLC","issue":"8","license":[{"start":{"date-parts":[[2014,3,19]],"date-time":"2014-03-19T00:00:00Z","timestamp":1395187200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2014,8]]},"DOI":"10.1007\/s00034-014-9749-x","type":"journal-article","created":{"date-parts":[[2014,3,18]],"date-time":"2014-03-18T11:26:20Z","timestamp":1395141980000},"page":"2625-2641","source":"Crossref","is-referenced-by-count":10,"title":["Energy Efficient Low Area Error Tolerant Adder with Higher Accuracy"],"prefix":"10.1007","volume":"33","author":[{"given":"R.","family":"Sakthivel","sequence":"first","affiliation":[]},{"given":"Harish M.","family":"Kittur","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2014,3,19]]},"reference":[{"key":"9749_CR1","doi-asserted-by":"crossref","first-page":"340","DOI":"10.1109\/IRETELC.1962.5407919","volume":"11","author":"O Bedrij","year":"1962","unstructured":"O. Bedrij, Carry select adder. IRE Transactions on Electronic Computers. 11, 340\u2013346 (1962)","journal-title":"IRE Transactions on Electronic Computers."},{"key":"9749_CR2","doi-asserted-by":"crossref","unstructured":"M.A. Breuer, Intelligible test techniques to support error-tolerance. Proc. Asian Test Symposium. pp. 386\u2013393 (2004)","DOI":"10.1109\/ATS.2004.51"},{"key":"9749_CR3","doi-asserted-by":"crossref","unstructured":"S. Cheemalavagu, P. Korkmaz, K.V. Palem, Ultra low energy computing via probabilistic algorithms and devices: CMOS device primitives and the energy-probability relationship. Proc. of International Conference on Solid State Devices and Materials, Tokyo. pp. 402\u2013403 (2004)","DOI":"10.7567\/SSDM.2004.P1-8L"},{"key":"9749_CR4","unstructured":"I.S. Chong, A. Ortega, Hardware testing for error tolerant multimedia compression based on linear transforms. Proc. of Defect and Fault Tolerance in VLSI System Symposium. pp. 523\u2013531 (2005)"},{"key":"9749_CR5","unstructured":"H. Chung, A. Ortega, Analysis and testing for error tolerant motion estimation. Proc. of Defect and Fault Tolerance in VLSI System Symposium. pp. 514\u2013522 (2005)."},{"key":"9749_CR6","doi-asserted-by":"crossref","unstructured":"T.Y. Hsieh, K.J. Lee, M.A. Breuer, Reduction of detected acceptable faults for yield improvement via error-tolerance. Proc. of Design Automation and Test Eur. Conf. Exhib. pp. 1\u20136 (2007).","DOI":"10.1109\/DATE.2007.364530"},{"key":"9749_CR7","volume-title":"Low-Voltage, Low-Power VLSI Subsystems","author":"Y Kiat-Seng","year":"2005","unstructured":"Y. Kiat-Seng, R. Kaushik, Low-Voltage, Low-Power VLSI Subsystems (McGraw-Hill, New York, 2005)"},{"key":"9749_CR8","unstructured":"K.J. Lee, T.Y. Hsieh, M.A. Breuer, A novel testing methodology based on error-rate to support error-tolerance. Proc. of International Test Conference. pp. 1136\u20131144 (2005)"},{"key":"9749_CR9","first-page":"691","volume":"10","author":"M Lehman","year":"1962","unstructured":"M. Lehman, N. Burla, Skip techniques for high-speed carry propagation in binary arithmetic units. IRE Trans. Electron. Comput. 10, 691\u2013698 (1962)","journal-title":"IRE Trans. Electron. Comput."},{"key":"9749_CR10","doi-asserted-by":"crossref","first-page":"67","DOI":"10.1109\/JRPROC.1961.287779","volume":"49","author":"O MacSorley","year":"1961","unstructured":"O. MacSorley, High speed arithmetic in binary computers. IRE Proc. 49, 67\u201391 (1961)","journal-title":"IRE Proc."},{"key":"9749_CR11","unstructured":"A.B. Melvin, Let\u2019s think analog. Proc. of the IEEE Computer Society Annual Symposium on VLSI. pp. 2\u20135 (2005)"},{"key":"9749_CR12","doi-asserted-by":"crossref","unstructured":"A.B. Melvin, Z. Haiyang, Error-tolerance and multi-media. Proc. of the International Conference on Intelligent Information Hiding and Multimedia, Signal Processing. pp. 521\u2013524 (2006)","DOI":"10.1109\/IIH-MSP.2006.265055"},{"issue":"9","key":"9749_CR13","doi-asserted-by":"crossref","first-page":"1123","DOI":"10.1109\/TC.2005.145","volume":"54","author":"KV Palem","year":"2005","unstructured":"K.V. Palem, Energy aware computing through probabilistic switching: a study of limits. IEEE Trans. Comput. 54(9), 1123\u20131137 (2005)","journal-title":"IEEE Trans. Comput."},{"issue":"2","key":"9749_CR14","first-page":"235","volume":"3","author":"AS Prabu","year":"2012","unstructured":"A.S. Prabu, V. Elakya, A. Andamuthu, N. Vignesh, Design of 64 bit error tolerant adder. Int. J. Adv. Res. Eng. Technol. 3(2), 235\u2013247 (2012)","journal-title":"Int. J. Adv. Res. Eng. Technol."},{"key":"9749_CR15","doi-asserted-by":"crossref","unstructured":"M.A. Raheem, H. Gupta, K. Fatima, O. Adil, A high speed reversible low power error tolerant adder. Proc. of Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PRIMEASIA), Hydrabad. pp. 178\u2013183 (2012)","DOI":"10.1109\/PrimeAsia.2012.6458649"},{"key":"9749_CR16","doi-asserted-by":"crossref","unstructured":"R. Sakthivel, K. Sravanthi, H.M. Kittur, Low power energy efficient pipelined multiply-accumulate architecture. Proc. of the International Conference on Advances in Computing, Communications and Informatics, ACM, New York. pp. 226\u2013231 (2012)","DOI":"10.1145\/2345396.2345434"},{"key":"9749_CR17","first-page":"3038","volume":"2013","author":"M Weber","year":"2013","unstructured":"M. Weber, M. Putic, H. Zhang, J. Lach, J. Huang, Balancing adder for error tolerant applications. Circuits and systems (ISCAS). IEEE Int. Symp. USA 2013, 3038\u20133041 (2013)","journal-title":"IEEE Int. Symp. USA"},{"key":"9749_CR18","doi-asserted-by":"crossref","unstructured":"N. Zhu, W.L. Goh, K.S. Yeo, An enhanced low-power high-speed adder for error-tolerant application. Proc. of the International Symposium on Integrated Circuits, Singapore. pp. 69\u201372 (2009)","DOI":"10.1109\/SOCDC.2010.5682905"},{"issue":"8","key":"9749_CR19","doi-asserted-by":"crossref","first-page":"1225","DOI":"10.1109\/TVLSI.2009.2020591","volume":"18","author":"N Zhu","year":"2010","unstructured":"N. Zhu, W.L. Goh, W. Zhang, K.S. Yeo, Z.H. Kong, Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing. IEEE Trans. Very Large Scale Integr. Syst. 18(8), 1225\u20131229 (2010)","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-014-9749-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s00034-014-9749-x\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-014-9749-x","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,2]],"date-time":"2025-05-02T02:42:55Z","timestamp":1746153775000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s00034-014-9749-x"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,3,19]]},"references-count":19,"journal-issue":{"issue":"8","published-print":{"date-parts":[[2014,8]]}},"alternative-id":["9749"],"URL":"https:\/\/doi.org\/10.1007\/s00034-014-9749-x","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"type":"print","value":"0278-081X"},{"type":"electronic","value":"1531-5878"}],"subject":[],"published":{"date-parts":[[2014,3,19]]}}}