{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,2]],"date-time":"2025-05-02T20:40:03Z","timestamp":1746218403429,"version":"3.40.4"},"reference-count":35,"publisher":"Springer Science and Business Media LLC","issue":"10","license":[{"start":{"date-parts":[[2014,5,7]],"date-time":"2014-05-07T00:00:00Z","timestamp":1399420800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2014,10]]},"DOI":"10.1007\/s00034-014-9799-0","type":"journal-article","created":{"date-parts":[[2014,5,6]],"date-time":"2014-05-06T11:27:10Z","timestamp":1399375630000},"page":"3165-3193","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Method for Designing Efficient Mixed Radix Multipliers"],"prefix":"10.1007","volume":"33","author":[{"given":"H.","family":"Pettenghi","sequence":"first","affiliation":[]},{"given":"F.","family":"Pratas","sequence":"additional","affiliation":[]},{"given":"L.","family":"Sousa","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2014,5,7]]},"reference":[{"key":"9799_CR1","unstructured":"H. Al-Twaijry, M.J. Flynn, Performance\/area tradeoffs in Booth multipliers (Technical Report, Stanford, CA, USA, 1995)"},{"issue":"6","key":"9799_CR2","doi-asserted-by":"crossref","first-page":"769","DOI":"10.1109\/TC.2004.2","volume":"53","author":"J-C Bajard","year":"2004","unstructured":"J.-C. Bajard, L. Imbert, A full RNS implementation of RSA. IEEE Trans. Compu. 53(6), 769\u2013774 (2004)","journal-title":"IEEE Trans. Compu."},{"key":"9799_CR3","doi-asserted-by":"crossref","unstructured":"J. Bajard, M. Kaihara, T. Plantard, Selected RNS bases for modular multiplication, IEEE Symposium on Computer Arithmetic, pp. 25\u201332 (2009)","DOI":"10.1109\/ARITH.2009.20"},{"key":"9799_CR4","doi-asserted-by":"crossref","first-page":"597","DOI":"10.1109\/CCECE.2002.1013009","volume":"2","author":"N Besli","year":"2002","unstructured":"N. Besli, R. Deshmukh, A $$54\\times 54$$ 54 \u00d7 54 -bit multiplier with a new Redundant Binary Booth $$^{\\prime }$$ \u2032 s encoding. IEEE Can. Conf. Electr. Comput. Eng. 2, 597\u2013602 (2002)","journal-title":"IEEE Can. Conf. Electr. Comput. Eng."},{"key":"9799_CR5","doi-asserted-by":"crossref","first-page":"236","DOI":"10.1093\/qjmam\/4.2.236","volume":"4","author":"AD Booth","year":"1951","unstructured":"A.D. Booth, A signed binary multiplication technique. Q. J. Mech. Appl. Math. 4, 236\u2013240 (1951)","journal-title":"Q. J. Mech. Appl. Math."},{"key":"9799_CR6","doi-asserted-by":"crossref","unstructured":"R. Chaves, L. Sousa, $$\\{2^n+1, 2^{n+k}, 2^n-1\\}$$ { 2 n + 1 , 2 n + k , 2 n - 1 } : A New RNS Moduli Set Extension, in IEEE Euromicro Symposium on Digital System Design: Architectures (Methods and Tools, IEEE Computer Society, 2004, pp. 210\u2013217","DOI":"10.1109\/DSD.2004.1333279"},{"issue":"8","key":"9799_CR7","doi-asserted-by":"crossref","first-page":"656","DOI":"10.1109\/82.618039","volume":"44","author":"B Cherkauer","year":"1997","unstructured":"B. Cherkauer, E. Friedman, A hybrid radix-4\/radix-8 low power signed multiplier architecture. IEEE Trans. Circuits Syst. II 44(8), 656\u2013659 (1997)","journal-title":"IEEE Trans. Circuits Syst. II"},{"key":"9799_CR8","unstructured":"E. Costa, S. Bampi, J. Monteiro, A new architecture for signed radix- $$2^m$$ 2 m pure array multipliers, IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 112\u2013117, (2002)."},{"key":"9799_CR9","volume-title":"Series in microelectronics","author":"A Curiger","year":"1993","unstructured":"A. Curiger, VLSI architectures for computations in finite rings and fields, Series in microelectronics (Hartung-Gorre, Konstanz, 1993)"},{"key":"9799_CR10","doi-asserted-by":"crossref","unstructured":"A. Efthymiou, W. Suntiamorntut, J. Garside, L. Brackenbury, An asynchronous, iterative implementation of the original booth multiplication algorithm, International Symposium on Asynchronous Circuits and Systems, pp. 207\u2013215 (2004).","DOI":"10.1109\/ASYNC.2004.1299304"},{"key":"9799_CR11","volume-title":"Advanced computer arithmetic design","author":"M Flynn","year":"2001","unstructured":"M. Flynn, S. Oberman, Advanced computer arithmetic design (Wiley, New York, 2001)"},{"key":"9799_CR12","doi-asserted-by":"crossref","unstructured":"M. Fonseca, E. Costa, S. Bampi, J. Monteiro, Design of a Radix- $$2^m$$ 2 m Hybrid Array Multiplier Using Carry Save Adder, Symposium on Integrated Circuits and Systems Design, pp. 172\u2013177 (2005).","DOI":"10.1109\/SBCCI.2005.4286852"},{"key":"9799_CR13","doi-asserted-by":"crossref","unstructured":"W.L. Gallagher, E.E. Swartzlander, High radix booth multipliers using reduced area adder trees. Conference Record of the Twenty-Eighth Asilomar Conference on Signals, Systems and Computers 1, 545\u2013549 (1994)","DOI":"10.1109\/ACSSC.1994.471512"},{"issue":"9","key":"9799_CR14","doi-asserted-by":"crossref","first-page":"1229","DOI":"10.1109\/4.149426","volume":"27","author":"G Goto","year":"1992","unstructured":"G. Goto, T. Sato, M. Nakajima, T. Sukemura, A $$54\\times 54$$ 54 \u00d7 54 -b regularly structured tree multiplier. IEEE J. Solid-State Circuits 27(9), 1229\u20131236 (1992)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"5","key":"9799_CR15","doi-asserted-by":"crossref","first-page":"716","DOI":"10.1109\/TCSVT.2005.846436","volume":"15","author":"D Guevorkian","year":"2005","unstructured":"D. Guevorkian, A. Launiainen, V. Lappalainen, P. Liuha, K. Punkka, A method for designing high-radix multiplier-based processing units for multimedia applications. IEEE Trans. Circuits Syst. Video Technol. 15(5), 716\u2013725 (2005)","journal-title":"IEEE Trans. Circuits Syst. Video Technol."},{"key":"9799_CR16","doi-asserted-by":"crossref","unstructured":"F. Liang, J. Liang, Z. Shao, S. Lei, A hybrid multiplier architecture using partially redundant booth algorithm, international workshop on electron devices and semiconductor technology, pp. 202\u2013205 (2007)","DOI":"10.1109\/EDST.2007.4289810"},{"issue":"3","key":"9799_CR17","doi-asserted-by":"crossref","first-page":"333","DOI":"10.1109\/12.660169","volume":"47","author":"Y Ma","year":"1998","unstructured":"Y. Ma, A simplified architecture for module ( $$2^{n}+1$$ 2 n + 1 ) multiplication. IEEE Trans. Comput. 47(3), 333\u2013337 (1998)","journal-title":"IEEE Trans. Comput."},{"issue":"49","key":"9799_CR18","doi-asserted-by":"crossref","first-page":"67","DOI":"10.1109\/JRPROC.1961.287779","volume":"1","author":"O Mac Sorley","year":"1961","unstructured":"O. Mac Sorley, High speed arithmetic in binary computers. Proc. IRE 1(49), 67\u201391 (1961)","journal-title":"Proc. IRE"},{"issue":"6","key":"9799_CR19","doi-asserted-by":"crossref","first-page":"773","DOI":"10.1109\/4.509863","volume":"31","author":"H Makino","year":"1996","unstructured":"H. Makino, Y. Nakase, H. Suzuki, H. Morinaka, H. Shinohara, K. Mashiko, An 8.8-ns $$54\\times 54$$ 54 \u00d7 54 -bit multiplier with high speed redundant binary architecture. IEEE J. Solid-State Circuits 31(6), 773\u2013783 (1996)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"9799_CR20","doi-asserted-by":"crossref","unstructured":"J. Mori, M. Nagamatsu, M. Hirano, S. Tanaka, M. Noda, Y. Toyoshima, K. Hashimoto, H. Hayashida, K. Maeguchi, A 10 ns $$54\\times 54$$ 54 \u00d7 54 -bit parallel structured full array multiplier with $$0.5\\mu $$ 0.5 \u03bc m CMOS technology, Symposium on VLSI Circuits, Digest of Technical Papers, pp. 125\u2013126, (1990).","DOI":"10.1109\/VLSIC.1990.111127"},{"key":"9799_CR21","doi-asserted-by":"crossref","unstructured":"R. Muralidharan, C.-H. Chang, Fast hard multiple generators for Radix-8 booth encoded modulo $$2^{n}-1$$ 2 n - 1 and modulo $$2^{n}+1$$ 2 n + 1 multipliers, IEEE International Symposium on Circuits and Systems, pp. 717\u2013720 (2010)","DOI":"10.1109\/ISCAS.2010.5537480"},{"key":"9799_CR22","doi-asserted-by":"crossref","unstructured":"R. Muralidharan, C.-H. Chang, A simple radix-4 booth encoded modulo $$2^{n}+1$$ 2 n + 1 multiplier, IEEE International Symposium on Circuits and Systems, pp. 1163\u20131166 (2011)","DOI":"10.1109\/ISCAS.2011.5937775"},{"issue":"5","key":"9799_CR23","doi-asserted-by":"crossref","first-page":"982","DOI":"10.1109\/TCSI.2010.2092133","volume":"58","author":"R Muralidharan","year":"2011","unstructured":"R. Muralidharan, C.-H. Chang, Radix-8 booth encoded modulo multipliers with adaptive delay for high dynamic range residue number system. IEEE Trans. Circuits Syst. I 58(5), 982\u2013993 (2011)","journal-title":"IEEE Trans. Circuits Syst. I"},{"issue":"10","key":"9799_CR24","doi-asserted-by":"crossref","first-page":"2263","DOI":"10.1109\/TCSI.2012.2185334","volume":"59\u2013I","author":"R Muralidharan","year":"2012","unstructured":"R. Muralidharan, C.-H. Chang, Area-power efficient modulo $$2^n-1$$ 2 n - 1 and modulo $$2^n+1$$ 2 n + 1 multipliers for $$\\{2^n-1, 2^n, 2^n+1\\}$$ { 2 n - 1 , 2 n , 2 n + 1 } based RNS. IEEE Trans. Circuits Syst. 59\u2013I(10), 2263\u20132274 (2012)","journal-title":"IEEE Trans. Circuits Syst."},{"key":"9799_CR25","first-page":"1","volume":"99","author":"R Muralidharan","year":"2013","unstructured":"R. Muralidharan, C.-H. Chang, Radix-4 and radix-8 booth encoded multi-modulus multipliers. IEEE Trans. Circuits Syst. I 99, 1\u201313 (2013)","journal-title":"IEEE Trans. Circuits Syst. I"},{"issue":"2","key":"9799_CR26","doi-asserted-by":"crossref","first-page":"494","DOI":"10.1109\/4.52175","volume":"25","author":"M Nagamatsu","year":"1990","unstructured":"M. Nagamatsu, S. Tanaka, J. Mori, K. Hirano, T. Noguchi, K. Hatanaka, A 15-ns $$32\\times 32$$ 32 \u00d7 32 -b CMOS multiplier with an improved parallel structure. IEEE J. Solid-State Circuits 25(2), 494\u2013497 (1990)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"9799_CR27","doi-asserted-by":"crossref","unstructured":"L. Pieper, E. Costa, S. Almeida, S. Bampi, J. Monteiro, Efficient dedicated multiplication blocks for 2 $$^{\\prime }$$ \u2032 s complement Radix-16 and Radix-256 array multipliers, International Conference on Signals, Circuits and Systems, pp. 1\u20136 (2008)","DOI":"10.1109\/ICSCS.2008.4746936"},{"issue":"1","key":"9799_CR28","doi-asserted-by":"crossref","first-page":"68","DOI":"10.1109\/12.250610","volume":"43","author":"S Piestrak","year":"1994","unstructured":"S. Piestrak, Design of residue generators and multioperand modular adders using carry-save adders. IEEE Trans. Comput. 43(1), 68\u201377 (1994)","journal-title":"IEEE Trans. Comput."},{"key":"9799_CR29","unstructured":"K. Ramamohan Reddy, V. Ramesh, C. Aslam, Design of modulo $$2^{n}-1$$ 2 n - 1 multiplier Based on Radix-8 Booth Algorithm using Residue Number System, Int. J. Eng. Res. Technol. 1 (6), (2012)."},{"issue":"1","key":"9799_CR30","doi-asserted-by":"crossref","first-page":"152","DOI":"10.1016\/j.mejo.2007.10.006","volume":"39","author":"GA Ruiz","year":"2008","unstructured":"G.A. Ruiz, M. Granda, Efficient implementation of $$3\\times $$ 3 \u00d7 for Radix-8 encoding. Microelectr. J. 39(1), 152\u2013159 (2008)","journal-title":"Microelectr. J."},{"issue":"6","key":"9799_CR31","doi-asserted-by":"crossref","first-page":"1166","DOI":"10.1109\/TCSI.2005.849143","volume":"52","author":"L Sousa","year":"2005","unstructured":"L. Sousa, R. Chaves, A universal architecture for designing efficient modulo $$2^{n}+1$$ 2 n + 1 multipliers. IEEE Trans. Circuits Syst. I 52(6), 1166\u20131178 (2005)","journal-title":"IEEE Trans. Circuits Syst. I"},{"key":"9799_CR32","volume-title":"Residue arithmetic and its applications to computer technology","author":"N Szabo","year":"1967","unstructured":"N. Szabo, Residue arithmetic and its applications to computer technology (McGraw-Hill, New York, 1967)"},{"key":"9799_CR33","unstructured":"Virtual Silicon Technology Inc: UMC high density standards cells library $$-$$ - 0.13 $$\\mu $$ \u03bc m CMOS process v2.3."},{"issue":"3","key":"9799_CR34","doi-asserted-by":"crossref","first-page":"241","DOI":"10.1007\/BF00929618","volume":"14","author":"Z Wang","year":"1996","unstructured":"Z. Wang, G.A. Jullien, W.C. Miller, An efficient tree architecture for modulo 2n+1 multiplication. VLSI Signal Process. 14(3), 241\u2013248 (1996)","journal-title":"VLSI Signal Process."},{"key":"9799_CR35","doi-asserted-by":"crossref","unstructured":"R. Zimmermann, Efficient VLSI implementation of modulo ( $$2^{n}\\pm 1$$ 2 n \u00b1 1 ) addition and multiplication, IEEE Symposium on Computer Arithmetic, pp. 158\u2013167 (1999)","DOI":"10.1109\/ARITH.1999.762841"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-014-9799-0.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s00034-014-9799-0\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-014-9799-0","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,2]],"date-time":"2025-05-02T20:22:39Z","timestamp":1746217359000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s00034-014-9799-0"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,5,7]]},"references-count":35,"journal-issue":{"issue":"10","published-print":{"date-parts":[[2014,10]]}},"alternative-id":["9799"],"URL":"https:\/\/doi.org\/10.1007\/s00034-014-9799-0","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"type":"print","value":"0278-081X"},{"type":"electronic","value":"1531-5878"}],"subject":[],"published":{"date-parts":[[2014,5,7]]}}}