{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,10]],"date-time":"2025-12-10T08:36:55Z","timestamp":1765355815753},"reference-count":35,"publisher":"Springer Science and Business Media LLC","issue":"11","license":[{"start":{"date-parts":[[2014,5,15]],"date-time":"2014-05-15T00:00:00Z","timestamp":1400112000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2014,11]]},"DOI":"10.1007\/s00034-014-9811-8","type":"journal-article","created":{"date-parts":[[2014,5,14]],"date-time":"2014-05-14T10:45:57Z","timestamp":1400064357000},"page":"3499-3526","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":9,"title":["Series Expansion based Efficient Architectures for Double Precision Floating Point Division"],"prefix":"10.1007","volume":"33","author":[{"given":"Manish Kumar","family":"Jaiswal","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ray C. C.","family":"Cheung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Balakrishnan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kolin","family":"Paul","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2014,5,15]]},"reference":[{"key":"9811_CR1","unstructured":"Altera: Stratix II vs. Virtex-4 Density Comparison, White Paper (2005). http:\/\/www.altera.com\/literature\/wp\/wpstxiixlnx"},{"key":"9811_CR2","doi-asserted-by":"crossref","first-page":"34","DOI":"10.1147\/rd.111.0034","volume":"11","author":"SF Anderson","year":"1967","unstructured":"S.F. Anderson, J.G. Earle, R.E. Goldschmidt, D.M. Powers, The IBM system\/360 model 91: floating-point execution unit. IBM J. Res. Dev. 11, 34\u201353 (1967). doi: 10.1147\/rd.111.0034","journal-title":"IBM J. Res. Dev."},{"key":"9811_CR3","doi-asserted-by":"crossref","unstructured":"E. Antelo, T. Lang, P. Montuschi, A. Nannarelli, Low latency digit-recurrence reciprocal and square-root reciprocal algorithm and architecture, in 17th IEEE Symposium on Computer Arithmetic (2005), pp. 147\u2013154. doi: 10.1109\/ARITH.2005.29","DOI":"10.1109\/ARITH.2005.29"},{"key":"9811_CR4","unstructured":"V. Daga, G. Govindu, V. Prasanna, S. Gangadharpalli, V. Sridhar, Floating-point based block lu decomposition on FPGAs, in Proceedings of the 2004 International Conference on Engineering Reconfigurable Systems and Architectures (ERSA) (2004), pp. 276\u2013279"},{"issue":"1","key":"9811_CR5","doi-asserted-by":"crossref","first-page":"42","DOI":"10.29292\/jics.v5i1.309","volume":"5","author":"MM Daniel","year":"2010","unstructured":"M.M. Daniel, F.S. Diego, H.L. Carlos, A.R. Mauricio, Tradeoff of FPGA design of a floating-point library for arithmeitic operators. J. Integr. Circuits Syst. 5(1), 42\u201352 (2010)","journal-title":"J. Integr. Circuits Syst."},{"key":"9811_CR6","doi-asserted-by":"crossref","unstructured":"R. Goldberg, G. Even, P.M Seidel, An FPGA implementation of pipelined multiplicative division with IEEE Rounding, in 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2007 (2007), pp. 185\u2013196. doi: 10.1109\/FCCM.2007.59","DOI":"10.1109\/FCCM.2007.59"},{"key":"9811_CR7","unstructured":"R.E. Goldschmidt, Application of Division by Convergence (Masters thesis, Massachusetts Institute of Technology, 1964)"},{"key":"9811_CR8","doi-asserted-by":"crossref","unstructured":"G. Govindu, L. Zhuo, S. Choi, V. Prasanna, Analysis of high-performance floating-point arithmetic on FPGAs, in Proceedings of 18th International Parallel and Distributed Processing Symposium, IEEE (2004), pp. 149\u2013156. doi: 10.1109\/IPDPS.2004.1303135","DOI":"10.1109\/IPDPS.2004.1303135"},{"key":"9811_CR9","unstructured":"G. Govindu, R. Scrofano, V.K. Prasanna, A library of parameterizable floating-point cores for fpgas and their application to scientific computing, in Proceedings of the International Conference on Engineering Reconfigurable Systems and Algorithms, IEEE Computer Society (2005), pp. 137\u2013148"},{"key":"9811_CR10","doi-asserted-by":"crossref","unstructured":"K.S. Hemmert, K.D. Underwood, Open source high performance floating-point modules, in 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM-06) (2006), pp. 349\u2013350. doi: 10.1109\/FCCM.2006.54","DOI":"10.1109\/FCCM.2006.54"},{"issue":"1","key":"9811_CR11","doi-asserted-by":"crossref","first-page":"115","DOI":"10.1109\/TVLSI.2007.891099","volume":"15","author":"KS Hemmert","year":"2007","unstructured":"K.S. Hemmert, K.D. Underwood, Floating-point divider design for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 15(1), 115\u2013118 (2007). doi: 10.1109\/TVLSI.2007.891099","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"issue":"3","key":"9811_CR12","doi-asserted-by":"crossref","first-page":"11:1","DOI":"10.1145\/1839480.1839481","volume":"3","author":"KS Hemmert","year":"2010","unstructured":"K.S. Hemmert, K.D. Underwood, Fast, efficient floating-point adders and multipliers for FPGAs. ACM Trans. Reconfig. Technol. Syst. 3(3), 11:1\u201311:30 (2010). doi: 10.1145\/1839480.1839481","journal-title":"ACM Trans. Reconfig. Technol. Syst."},{"key":"9811_CR13","unstructured":"M. Huang, L. Wang, T. El-Ghazawi, Accelerating double precision floating-point Hessenberg reduction on FPGA and multicore architectures, in Symposium on Application Accelerators in High, Performance Computing (SAAHPC\u201910) (2010)"},{"key":"9811_CR14","doi-asserted-by":"crossref","unstructured":"P. Hung, H. Fahmy, O. Mencer, M. Flynn, Fast division algorithm with a small lookup table, in Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999, vol. 2 (1999), pp. 1465\u20131468. doi: 10.1109\/ACSSC.1999.831992","DOI":"10.1109\/ACSSC.1999.831992"},{"key":"9811_CR15","doi-asserted-by":"crossref","unstructured":"IEEE standard for Binary Floating-Point Arithmetic, ANSI\/IEEE Std 754-1985 (1985). doi: 10.1109\/IEEESTD.1985.82928","DOI":"10.1109\/IEEESTD.1985.82928"},{"key":"9811_CR16","doi-asserted-by":"crossref","unstructured":"IEEE Standard for Floating-Point Arithmetic, Tech. rep. (2008). doi: 10.1109\/IEEESTD.2008.4610935","DOI":"10.1109\/IEEESTD.2008.4610935"},{"key":"9811_CR17","doi-asserted-by":"crossref","unstructured":"M.K. Jaiswal, R.C.C. Cheung, High performance reconfigurable architecture for double precision floating point division, in 8th International Symposium on Applied Reconfigurable Computing (ARC-2012). LNCS (Springer, Hong Kong, 2012), pp. 302\u2013313.","DOI":"10.1007\/978-3-642-28365-9_25"},{"key":"9811_CR18","doi-asserted-by":"crossref","first-page":"60","DOI":"10.1109\/TC.2011.24","volume":"61","author":"MK Jaiswal","year":"2012","unstructured":"M.K. Jaiswal, N. Chandrachoodan, FPGA-based high-performance and scalable block LU decomposition architecture. IEEE Trans.Comput. 61, 60\u201372 (2012). doi: 10.1109\/TC.2011.24","journal-title":"IEEE Trans.Comput."},{"issue":"4","key":"9811_CR19","first-page":"489","volume":"53","author":"JC Jeong","year":"2004","unstructured":"J.C. Jeong, W.C. Park, W. Jeong, T.D. Han, M.K. Lee, A cost-effective pipelined divider with a small lookup table. IEEE Trans. Comput. 53(4), 489\u2013495 (2004). doi: 10.1109\/TC.2004.1268407","journal-title":"IEEE Trans. Comput."},{"issue":"3","key":"9811_CR20","doi-asserted-by":"crossref","first-page":"151","DOI":"10.1016\/j.parco.2008.12.004","volume":"35","author":"JS Meredith","year":"2009","unstructured":"J.S. Meredith, G. Alvarez, T.A. Maier, T.C. Schulthess, J.S. Vetter, Accuracy and performance of graphics processors: a quantum Monte Carlo application case study. Parallel Comput. 35(3), 151\u2013163 (2009). doi: 10.1016\/j.parco.2008.12.004","journal-title":"Parallel Comput."},{"issue":"6","key":"9811_CR21","doi-asserted-by":"crossref","first-page":"317","DOI":"10.1049\/ip-cdt:19941386","volume":"141","author":"P Montuschi","year":"1994","unstructured":"P. Montuschi, L. Ciminiera, A. Giustina, Division unit with Newton\u2013Raphson approximation and digit-by-digit refinement of the quotient. IEEE Proc. Comput. Digit. Tech. 141(6), 317\u2013324 (1994)","journal-title":"IEEE Proc. Comput. Digit. Tech."},{"issue":"8","key":"9811_CR22","doi-asserted-by":"crossref","first-page":"833","DOI":"10.1109\/12.609274","volume":"46","author":"SF Obermann","year":"1997","unstructured":"S.F. Obermann, M.J. Flynn, Division algorithms and implementations. IEEE Trans. Comput. 46(8), 833\u2013854 (1997). doi: 10.1109\/12.609274","journal-title":"IEEE Trans. Comput."},{"key":"9811_CR23","doi-asserted-by":"crossref","unstructured":"H. Parizi, A. Niktash, A. Kamalizad, N. Bagherzadeh, A reconfigurable architecture for wireless communication systems. in Third International Conference on Information Technology: New Generations (2006), 250\u2013255. doi: 10.1109\/ITNG.2006.16","DOI":"10.1109\/ITNG.2006.16"},{"key":"9811_CR24","doi-asserted-by":"crossref","unstructured":"B. Pasca, Correctly rounded floating-point division for dsp-enabled FPGAs, in 22nd International Conference on Field Programmable Logic and Applications (FPL 2012) (2012), pp. 249\u2013254. doi: 10.1109\/FPL.2012.6339189","DOI":"10.1109\/FPL.2012.6339189"},{"key":"9811_CR25","unstructured":"S. Paschalakis, P. Lee, Double precision floating-point arithmetic on FPGAs, in 2nd IEEE International Conference on Field Programmable Techonology (FPT\u201903) (2003), pp. 352\u2013358"},{"key":"9811_CR26","doi-asserted-by":"crossref","unstructured":"R. Strzodka, D. G\u00f6ddeke, Pipelined mixed precision algorithms on FPGAs for fast and accurate PDE solvers from low precision components, in 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM \u201906 (2006), pp. 259\u2013270. doi: 10.1109\/FCCM.2006.57","DOI":"10.1109\/FCCM.2006.57"},{"key":"9811_CR27","first-page":"21","volume":"4","author":"DW Sweeney","year":"1965","unstructured":"D.W. Sweeney, An analysis of floating-point addition. IBM Syst. 4, 21\u201342 (1965). doi: 10.1147\/sj.41.0031","journal-title":"IBM Syst."},{"key":"9811_CR28","doi-asserted-by":"crossref","unstructured":"A.J. Thakkar, A. Ejnioui, Pipelining of double precision floating point division and square root operations, in Proceedings of the 44th annual Southeast regional conference, ACM-SE 44 (ACM, New York, NY, 2006), pp. 488\u2013493. doi: 10.1145\/1185448.1185555","DOI":"10.1145\/1185448.1185555"},{"key":"9811_CR29","doi-asserted-by":"crossref","unstructured":"K. Underwood, FPGAs vs. CPUs: trends in peak floating-point performance, in Proceedings of the 2004 ACM\/SIGDA 12th international symposium on Field programmable gate arrays, FPGA \u201904 (ACM, New York, NY, 2004), pp. 171\u2013180. doi: 10.1145\/968280.968305","DOI":"10.1145\/968280.968305"},{"key":"9811_CR30","doi-asserted-by":"crossref","unstructured":"S.K. Venishetti, A. Akoglu, A highly parallel FPGA based IEEE-754 compliant double-precision binary floating-point multiplication algorithm. in International Conference on Field-Programmable Techonology (ICFPT 2007) (2007), pp. 145\u2013152. doi: 10.1109\/FPT.2007.4439243","DOI":"10.1109\/FPT.2007.4439243"},{"key":"9811_CR31","unstructured":"S.K. Venishetti, A. Akoglu, Highly parallel FPGA based IEEE-754 compliant double-precision floating-point division. in ERSA\u201908 (2008), pp. 159\u2013165"},{"key":"9811_CR32","doi-asserted-by":"crossref","unstructured":"X. Wang, S. Braganza, M. Leeser, Advanced components in the variable precision floating-point library, in 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM -06) (2006), pp. 249\u2013258. doi: 10.1109\/FCCM.2006.21","DOI":"10.1109\/FCCM.2006.21"},{"key":"9811_CR33","doi-asserted-by":"crossref","unstructured":"X. Wang, M. Leeser, Vfloat: A variable precision fixed- and floating-point library for reconfigurable hardware, ACM Trans. Reconfig. Technol. Syst. 3(3), 16:1\u201316:34 (2010). doi: 10.1145\/1839480.1839486 , 10.1145\/1839480.1839486","DOI":"10.1145\/1839480.1839486"},{"key":"9811_CR34","unstructured":"X. Wang, B.E. Nelson, Tradeoffs of designing floating-point division and square root on Virtex FPGAs. in 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM-2003) (2003), pp. 195\u2013203"},{"key":"9811_CR35","unstructured":"Xilinx, Xilinx Floating-Point IP Core. http:\/\/www.xilinx.com . Accessed 2014"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-014-9811-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s00034-014-9811-8\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-014-9811-8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T15:19:42Z","timestamp":1648999182000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s00034-014-9811-8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,5,15]]},"references-count":35,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2014,11]]}},"alternative-id":["9811"],"URL":"https:\/\/doi.org\/10.1007\/s00034-014-9811-8","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"value":"0278-081X","type":"print"},{"value":"1531-5878","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,5,15]]}}}