{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,10]],"date-time":"2025-10-10T07:02:57Z","timestamp":1760079777136},"reference-count":37,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2014,8,12]],"date-time":"2014-08-12T00:00:00Z","timestamp":1407801600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2015,2]]},"DOI":"10.1007\/s00034-014-9862-x","type":"journal-article","created":{"date-parts":[[2014,8,11]],"date-time":"2014-08-11T09:01:20Z","timestamp":1407747680000},"page":"459-482","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["A Low-Memory-Access Length-Adaptive Architecture for 2 $$^n$$ n -Point FFT"],"prefix":"10.1007","volume":"34","author":[{"given":"Kuan-Hung","family":"Chen","sequence":"first","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2014,8,12]]},"reference":[{"key":"9862_CR1","unstructured":"Artisan Component, TSMC 0.18- $$\\mu $$ \u03bc m process 1.8-volt SAGE-X standard cell library, Databook (2003)"},{"issue":"3","key":"9862_CR2","doi-asserted-by":"crossref","first-page":"380","DOI":"10.1109\/4.748190","volume":"34","author":"BM Baas","year":"1999","unstructured":"B.M. Baas, A low-power, high-performance 1,024-point FFT processor. IEEE J. Solid-State Circuits 34(3), 380\u2013387 (1999)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"9862_CR3","unstructured":"V. Baireddy, H. Khasnis, R. Mundhada, A 64\u20134,096 point FFT\/IFFT\/windowing processor for multi-standard ADSL\/VDSL applications, in Proceedings of the IEEE International Symposium on Signals, Systems and Electronics (2007), pp. 403\u2013405"},{"issue":"12","key":"9862_CR4","doi-asserted-by":"crossref","first-page":"1982","DOI":"10.1109\/29.45545","volume":"37","author":"G Bi","year":"1989","unstructured":"G. Bi, E.V. Jones, A pipelined FFT processor for word-sequential data. IEEE Trans. Acoust. Speech Signal Process. 37(12), 1982\u20131985 (1989)","journal-title":"IEEE Trans. Acoust. Speech Signal Process."},{"issue":"3","key":"9862_CR5","doi-asserted-by":"crossref","first-page":"300","DOI":"10.1109\/4.364445","volume":"30","author":"E Bidet","year":"1995","unstructured":"E. Bidet, D. Castelain, C. Joanblanq, P. Senn, A fast single-chip implementation of 8,192 complex point FFT. IEEE J. Solid-State Circuits 30(3), 300\u2013305 (1995)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"9862_CR6","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-2325-3","volume-title":"Low power digital CMOS design","author":"AP Chandrakasan","year":"1995","unstructured":"A.P. Chandrakasan, R.W. Brodersen, Low power digital CMOS design (Kluwer Academic Publishers, Boston, 1995)"},{"key":"9862_CR7","first-page":"129","volume":"2","author":"CK Chang","year":"2003","unstructured":"C.K. Chang, C.P. Hung, S.G. Chen, An efficient memory-based FFT architecture. Proc. IEEE Int. Symp. Circuits Syst. 2, 129\u2013132 (2003)","journal-title":"Proc. IEEE Int. Symp. Circuits Syst."},{"key":"9862_CR8","unstructured":"L.F. Chen, L.C. Chien, Y.H. Ma, C.H. Lee, Y.W. Lin, C.C. Lin, H.Y. Lin, T.Y. Hsu, C.Y. Lee, A 1.8\u00a0V 250\u00a0mW COFDM baseband receiver for DVB-T\/H applications, in Proceedings of the IEEE International Solid-State Circuits Conference (2006), pp. 262\u2013263"},{"issue":"1","key":"9862_CR9","doi-asserted-by":"crossref","first-page":"132","DOI":"10.1109\/TCSI.2008.926582","volume":"56","author":"KH Chen","year":"2009","unstructured":"K.H. Chen, Y.S. Chu, A spurious-power suppression technique for multimedia\/DSP applications. IEEE Trans. Circuits Syst. I 56(1), 132\u2013143 (2009)","journal-title":"IEEE Trans. Circuits Syst. I"},{"key":"9862_CR10","unstructured":"K.H. Chen, Y.S. Li, A multi-radix FFT processor using pipeline in memory-based architecture (PIMA) for DVB-T\/H systems, in Proceedings of the IEEE International Mixed Design of Integrated Circuits and Systems (2008), pp. 549\u2013554."},{"issue":"2","key":"9862_CR11","doi-asserted-by":"crossref","first-page":"146","DOI":"10.1109\/TCSII.2007.910771","volume":"55","author":"Y Chen","year":"2008","unstructured":"Y. Chen, Y.C. Tsao, Y.W. Lin, C.H. Lin, C.Y. Lee, An indexed-scaling pipelined FFT processor for OFDM-based WPAN applications. IEEE Trans. Circuits Syst. II 55(2), 146\u2013150 (2008)","journal-title":"IEEE Trans. Circuits Syst. II"},{"issue":"5","key":"9862_CR12","first-page":"87","volume":"5","author":"JW Cooley","year":"1965","unstructured":"J.W. Cooley, J.W. Tukey, An algorithm for the machine calculation of complex Fourier series. Math. Comput. 5(5), 87\u2013109 (1965)","journal-title":"Math. Comput."},{"key":"9862_CR13","unstructured":"ETSI, Digital video broadcasting (DVB); Framing structure, channel coding and modulation for digital terrestrial television, ETSI EN 300 744 v1.5.1 (2004)"},{"key":"9862_CR14","unstructured":"ETSI, Digital video broadcasting (DVB); transmission systems for handheld terminals (DVB-H), ETSI EN 302 304 v1.1.1 (2004)"},{"issue":"10","key":"9862_CR15","doi-asserted-by":"crossref","first-page":"723","DOI":"10.1109\/82.199898","volume":"39","author":"JI Guo","year":"1992","unstructured":"J.I. Guo, C.M. Liu, C.W. Jen, The efficient memory-based VLSI array designs for DFT and DCT. IEEE Trans. Circuits Syst. II 39(10), 723\u2013733 (1992)","journal-title":"IEEE Trans. Circuits Syst. II"},{"key":"9862_CR16","unstructured":"S. He, M. Torkelson, Designing pipeline FFT processor for OFDM (de)modulation, in Proceedings of the IEEE International Symposium on Signals, Systems and Electronics (1998), pp. 257\u2013262"},{"issue":"8","key":"9862_CR17","doi-asserted-by":"crossref","first-page":"1752","DOI":"10.1109\/TCSI.2011.2180430","volume":"59","author":"SJ Huang","year":"2012","unstructured":"S.J. Huang, S.G. Chen, A high-throughput radix-16 FFT processor with parallel and normal input\/output ordering for IEEE 802.15.3c systems. IEEE Trans. Circuits Syst. I 59(8), 1752\u20131765 (2012)","journal-title":"IEEE Trans. Circuits Syst. I"},{"key":"9862_CR18","unstructured":"C. L. Hung, S. S. Long, and M. T. Shiue, A low-power and variable-length FFT design for flexible MIMO OFDM systems, Proceedings of the IEEE International Symposium on Circuits and Systems (2009), pp. 705\u2013708"},{"key":"9862_CR19","unstructured":"L. Jia, Y. Gao, J. Isoaho, H. Tenhunen, A new VLSI-oriented FFT algorithm and implementation, in Proceedings of the IEEE ASIC Conference (1998), pp. 337\u2013341"},{"key":"9862_CR20","volume-title":"Reuse Methodology Manual for System-on-a-Chip Designs","author":"M Keating","year":"2002","unstructured":"M. Keating, P. Bricaud, Reuse Methodology Manual for System-on-a-Chip Designs (Kluwer Academic Publishers, Dordrecht, 2002)"},{"issue":"4","key":"9862_CR21","doi-asserted-by":"crossref","first-page":"889","DOI":"10.1109\/TCSI.2006.888764","volume":"54","author":"HY Lee","year":"2007","unstructured":"H.Y. Lee, Y.C. Park, Balanced binary-tree decomposition for area-efficient pipelined FFT processing. IEEE Trans. Circuits Syst. I 54(4), 889\u2013900 (2007)","journal-title":"IEEE Trans. Circuits Syst. I"},{"key":"9862_CR22","unstructured":"H. Lee, M. Shin, A high-speed low-complexity two-parallel radix-2 $$^{4}$$ 4 FFT\/IFFT processor for UWB applications, in Proceedings of IEEE Asian Solid-State Circuits Conference (2007), pp. 284\u2013287"},{"key":"9862_CR23","unstructured":"W. Li, L. Wanhammar, A pipeline FFT processor, in Proceedings of the IEEE Workshop on Signal Processing Systems (1999), pp. 654\u2013662"},{"issue":"11","key":"9862_CR24","doi-asserted-by":"crossref","first-page":"2005","DOI":"10.1109\/JSSC.2004.835815","volume":"39","author":"YW Lin","year":"2004","unstructured":"Y.W. Lin, H.Y. Liu, C.Y. Lee, A dynamic scaling FFT processor for DVB-T applications. IEEE J. Solid-State Circuits 39(11), 2005\u20132013 (2004)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"8","key":"9862_CR25","doi-asserted-by":"crossref","first-page":"1726","DOI":"10.1109\/JSSC.2005.852007","volume":"40","author":"YW Lin","year":"2005","unstructured":"Y.W. Lin, H.Y. Liu, C.Y. Lee, A 1-GS\/s FFT\/IFFT processor for UWB applications. IEEE J. Solid-State Circuits 40(8), 1726\u20131735 (2005)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"4","key":"9862_CR26","doi-asserted-by":"crossref","first-page":"2072","DOI":"10.1109\/TCE.2010.5681074","volume":"56","author":"SY Lin","year":"2010","unstructured":"S.Y. Lin, C.L. Wei, M.D. Shieh, Low-cost FFT processor for DVB-T2 applications. IEEE Trans. Consum. Electron. 56(4), 2072\u20132079 (2010)","journal-title":"IEEE Trans. Consum. Electron."},{"key":"9862_CR27","first-page":"1989","volume":"4","author":"S Magar","year":"1988","unstructured":"S. Magar, S. Shen, G. Luikuo, M. Fleming, R. Aguilar, An application specific DSP chip set for 100\u00a0MHz data rate. Proc. Int. Conf. Acoust. Speech Signal Process. 4, 1989\u20131992 (1988)","journal-title":"Proc. Int. Conf. Acoust. Speech Signal Process."},{"issue":"3","key":"9862_CR28","doi-asserted-by":"crossref","first-page":"484","DOI":"10.1109\/JSSC.2003.822776","volume":"39","author":"K Maharatna","year":"2004","unstructured":"K. Maharatna, E. Grass, U. Jagdhold, A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM. IEEE J. Solid-State Circuits 39(3), 484\u2013493 (2004)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"9862_CR29","unstructured":"N. Miyamoto, L. Karnan, K. Maruo, K. Kotani, T. Ohmi, A small-area high-performance 512-point 2-dimensional FFT single-chip processor, in Proceedings of the IEEE European Solid-State Circuits Conference (2003), pp. 603\u2013606"},{"key":"9862_CR30","volume-title":"VLSI Digital Signal Processing Systems","author":"KK Parhi","year":"1999","unstructured":"K.K. Parhi, VLSI Digital Signal Processing Systems (Wiley-Interscience Publication, New York, 1999)"},{"key":"9862_CR31","doi-asserted-by":"crossref","unstructured":"A.A. Petrovsky, S.L. Shkredov, Automatic generation of split-radix 2\u20134 parallel-pipeline FFT processors: hardware reconfiguration and core optimization, in Proceedings of the IEEE International Symposium on Parallel Computing Electrical Engineering (2006), pp. 181\u2013186","DOI":"10.1109\/PARELEC.2006.18"},{"key":"9862_CR32","unstructured":"S. Qiao, Y. Hei, B. Wu, Y. Zhou, An area and power efficient FFT processor for UWB systems, in Proceedings of the IEEE Conference on Wireless Communications, Networking and Mobile Computing (2007), pp. 582\u2013585"},{"key":"9862_CR33","unstructured":"Virtual silicon preliminary data sheet on single-port\/dual-port\/two-port SRAM compiler for UMC 0.18 $$\\mu $$ \u03bc m (L180GII) (2004), pp. 1\u20133"},{"key":"9862_CR34","unstructured":"C. Wang, W.S. Gan, C.C. Jong, J. Luo, A low-cost 256-point FFT processor for portable speech and audio applications, in Proceedings of the IEEE International Symposium on Integrated Circuits (2007), pp. 81\u201384"},{"issue":"1","key":"9862_CR35","doi-asserted-by":"crossref","first-page":"28","DOI":"10.1109\/TCE.2005.1405695","volume":"51","author":"CC Wang","year":"2005","unstructured":"C.C. Wang, J.M. Huang, H.C. Cheng, A 2k\/8k mode small-area FFT processor for OFDM demodulation of DVB-T receivers. IEEE Trans. Consum. Electron. 51(1), 28\u201332 (2005)","journal-title":"IEEE Trans. Consum. Electron."},{"key":"9862_CR36","unstructured":"C.L. Wey, W.C. Tang, S.Y. Lin, Efficient memory-based architectures for digital video broadcasting automation and test, in Proceedings of the IEEE International Symposium VLSI Design (2007), pp. 1\u20134"},{"issue":"3","key":"9862_CR37","doi-asserted-by":"crossref","first-page":"864","DOI":"10.1109\/TSP.2002.806904","volume":"51","author":"WC Yeh","year":"2003","unstructured":"W.C. Yeh, C.W. Jen, High-speed and low-power split-radix FFT. IEEE Trans. Signal Process. 51(3), 864\u2013874 (2003)","journal-title":"IEEE Trans. Signal Process."}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-014-9862-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s00034-014-9862-x\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-014-9862-x","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,22]],"date-time":"2019-05-22T15:01:46Z","timestamp":1558537306000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s00034-014-9862-x"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,8,12]]},"references-count":37,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2015,2]]}},"alternative-id":["9862"],"URL":"https:\/\/doi.org\/10.1007\/s00034-014-9862-x","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"value":"0278-081X","type":"print"},{"value":"1531-5878","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,8,12]]}}}