{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,25]],"date-time":"2025-10-25T19:02:49Z","timestamp":1761418969726,"version":"3.41.0"},"reference-count":39,"publisher":"Springer Science and Business Media LLC","issue":"10","license":[{"start":{"date-parts":[[2015,3,5]],"date-time":"2015-03-05T00:00:00Z","timestamp":1425513600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2015,10]]},"DOI":"10.1007\/s00034-015-0009-5","type":"journal-article","created":{"date-parts":[[2015,3,4]],"date-time":"2015-03-04T08:24:02Z","timestamp":1425457442000},"page":"3121-3145","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":7,"title":["65-nm CMOS Voltage-to-Time Converter for 5-GS\/s Time-Based ADCs"],"prefix":"10.1007","volume":"34","author":[{"given":"Andrew R.","family":"Macpherson","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Leonid","family":"Belostotski","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"James W.","family":"Haslett","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2015,3,5]]},"reference":[{"issue":"8","key":"9_CR1","doi-asserted-by":"crossref","first-page":"1803","DOI":"10.1109\/JSSC.2006.876206","volume":"41","author":"A Abidi","year":"2006","unstructured":"A. Abidi, Phase noise and jitter in CMOS ring oscillators. IEEE J. Solid State Circuits 41(8), 1803\u20131816 (2006)","journal-title":"IEEE J. Solid State Circuits"},{"key":"9_CR2","doi-asserted-by":"crossref","unstructured":"W. Bennett, Spectra of quantized signals. Bell Syst. Tech. J. 27(3), 446\u2013472 (1948). http:\/\/www.alcatel-lucent.com\/bstj\/vol27-1948\/articles\/bstj27-3-446","DOI":"10.1002\/j.1538-7305.1948.tb01340.x"},{"issue":"10","key":"9_CR3","doi-asserted-by":"crossref","first-page":"2116","DOI":"10.1109\/JSSC.2010.2063630","volume":"45","author":"J Borremans","year":"2010","unstructured":"J. Borremans, K. Vengattaramane, V. Giannini, B. Debaillie, W. Van Thillo, J. Craninckx, A 86 MHz-12 GHz digital-intensive PLL for software-defined radios, Using a 6 fJ\/Step TDC in 40 nm digital CMOS. IEEE J. Solid State Circuits 45(10), 2116\u20132129 (2010)","journal-title":"IEEE J. Solid State Circuits"},{"issue":"2","key":"9_CR4","first-page":"78","volume":"5","author":"R Brodersen","year":"2013","unstructured":"R. Brodersen, Antiques from the innovations attic. IEEE Solid State Circuits Mag. 5(2), 78\u201379 (2013)","journal-title":"IEEE Solid State Circuits Mag."},{"key":"9_CR5","unstructured":"J. Bulzacchelli, D. Friedman, S. Naraghi, S. Rylov, A. Rylyakov, Z. Toprak-Deniz, Time-to-digital based analog-to-digital converter architecture (2011)"},{"issue":"3","key":"9_CR6","doi-asserted-by":"crossref","first-page":"529","DOI":"10.1109\/TCSI.2012.2215792","volume":"60","author":"A Homayoun","year":"2013","unstructured":"A. Homayoun, B. Razavi, Analysis of phase noise in phase\/frequency detectors. IEEE Trans. Circuits Syst. I Regul. Pap. 60(3), 529\u2013539 (2013)","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"issue":"2","key":"9_CR7","doi-asserted-by":"crossref","first-page":"384","DOI":"10.1109\/JSSC.2013.2289893","volume":"49","author":"A Homayoun","year":"2014","unstructured":"A. Homayoun, B. Razavi, Relation between delay line phase noise and ring oscillator phase noise. IEEE J. Solid State Circuits 49(2), 384\u2013391 (2014)","journal-title":"IEEE J. Solid State Circuits"},{"key":"9_CR8","unstructured":"W. Kester, MT-001: Taking the Mystery out of the Infamous Formula, \u201cSNR=6.02N + 1.76dB,\u201d and Why You Should Care. [Online] (2012). Analog Devices, REV. 0, 10\u201303-2005. http:\/\/www.analog.com\/static\/imported-files\/tutorials\/MT-001"},{"key":"9_CR9","unstructured":"J. Kim, S. Cho, A time-based analog-to-digital converter using a multi-phase voltage controlled oscillator. In IEEE International Symposium on Circuits and Systems (Kos, Greece 2006), pp. 3934\u20133937"},{"key":"9_CR10","doi-asserted-by":"crossref","unstructured":"P. Kinget, J. Kuppambatti, B. Vigraham, C.W. Hsu, Scaling analog circuits. In IEEE European Solid-State Circuits Conference (Bucharest,Romania, 2013), p. 32","DOI":"10.1109\/ESSCIRC.2013.6649064"},{"issue":"6","key":"9_CR11","doi-asserted-by":"crossref","first-page":"464","DOI":"10.1109\/TCSII.2009.2020947","volume":"56","author":"G Li","year":"2009","unstructured":"G. Li, Y. Tousi, A. Hassibi, E. Afshari, Delay-line-based analog-to-digital converters. IEEE Trans. Circuits Syst. II Exp. Br. 56(6), 464\u2013468 (2009)","journal-title":"IEEE Trans. Circuits Syst. II Exp. Br."},{"key":"9_CR12","unstructured":"A. Macpherson, A time-based 5GS\/s CMOS analog-to-digital converter. Ph.D. thesis, University of Calgary (2013)"},{"key":"9_CR13","doi-asserted-by":"crossref","unstructured":"A. Macpherson, J. Haslett, L. Belostotski, A 5GS\/s 4-bit time-based single-channel CMOS ADC for radio astronomy. In IEEE Custom Integrated Circuits Conference (San Jose, 2013), pp. 1\u20134","DOI":"10.1109\/CICC.2013.6658551"},{"key":"9_CR14","unstructured":"A. Macpherson, K. Townsend, J. Haslett, A 5GS\/s voltage-to-time converter in 90nm CMOS. In IEEE European Microwave Integrated Circuits Conference (Rome,Italy, 2009), pp. 254\u2013257"},{"key":"9_CR15","doi-asserted-by":"crossref","unstructured":"Y.J. Min, A. Abdullah, H.K. Kim, S.W. Kim, A 5-bit 500-MS\/s time-domain flash ADC in 0.18- $$\\mu $$ \u03bc m CMOS. In International Symposium on Integrated Circuits (Singapore, 2011), pp. 336\u2013339","DOI":"10.1109\/ISICir.2011.6131965"},{"key":"9_CR16","doi-asserted-by":"crossref","unstructured":"S. Naraghi, M. Courcy, M. Flynn, A 9b 14 $$\\mu $$ \u03bc W 0.06mm $$^2$$ 2 PPM ADC in 90nm digital CMOS. In IEEE International Solid-State Circuits Conference (San Francisco, 2009), pp. 168\u2013169","DOI":"10.1109\/ISSCC.2009.4977361"},{"issue":"4","key":"9_CR17","doi-asserted-by":"crossref","first-page":"961","DOI":"10.1109\/JSSC.2013.2293019","volume":"49","author":"T Oh","year":"2014","unstructured":"T. Oh, H. Venkatram, U. Moon, A time-based pipelined ADC using both voltage and time domain information. IEEE J. Solid-State Circuits 49(4), 961\u2013971 (2014)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"9_CR18","doi-asserted-by":"crossref","unstructured":"H. Pekau, A. Yousif, J. Haslett, A CMOS integrated linear voltage-to-pulse-delay-time converter for time based analog-to-digital converters. In IEEE International Symposium on Circuits and Systems (Kos,Greece, 2006), pp. 2373\u20132376","DOI":"10.1109\/ISCAS.2006.1693099"},{"key":"9_CR19","doi-asserted-by":"crossref","unstructured":"M. Park, M. Perrott, A VCO-based analog-to-digital converter with second-order sigma-delta noise shaping. In IEEE International Symposium on Circuits and Systems (Taipei, 2009), pp. 3130\u20133133","DOI":"10.1109\/ISCAS.2009.5118466"},{"key":"9_CR20","volume-title":"Digital Integrated Circuits\u2014A Design Perspective","author":"J Rabaey","year":"2004","unstructured":"J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits\u2014A Design Perspective, 2nd edn. (Prentice Hall, New Jersey, 2004)","edition":"2"},{"key":"9_CR21","doi-asserted-by":"crossref","unstructured":"W. Rao, P. Hanumolu, A deterministic background calibration technique for VCO-based ADCs. In Workshop on Advances in Analog Circuit and Design (Lisbon, 2014), pp. 1\u20134","DOI":"10.1109\/JSSC.2013.2293753"},{"key":"9_CR22","unstructured":"S. Rao, B. Young, A. Elshazly, W. Yin, N. Sasidhar, P. Hanumolu, A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation. In IEEE Symposium on VLSI Circuits (2011), pp. 270\u2013271"},{"issue":"8","key":"9_CR23","doi-asserted-by":"crossref","first-page":"1829","DOI":"10.1109\/JSSC.2013.2259031","volume":"48","author":"A Samarah","year":"2013","unstructured":"A. Samarah, A. Carusone, A digital phase-locked loop with calibrated coarse and stochastic fine TDC. IEEE J. Solid-State Circuits 48(8), 1829\u20131841 (2013)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"3","key":"9_CR24","doi-asserted-by":"crossref","first-page":"736","DOI":"10.1109\/JSSC.2011.2176609","volume":"47","author":"YH Seo","year":"2012","unstructured":"Y.H. Seo, J.S. Kim, H.J. Park, J.Y. Sim, A 1.25 ps resolution 8b cyclic TDC in 0.13 $$\\mu $$ \u03bc m CMOS. IEEE J. Solid-State Circuits 47(3), 736\u2013743 (2012)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"9_CR25","doi-asserted-by":"crossref","unstructured":"R. Staszewski, D. Leipold, C.M. Hung, P. Balsara, TDC-based frequency synthesizer for wireless applications. In IEEE Radio Frequency Integrated Circuits Symposium (Fort Worth, 2004), pp. 215\u2013218","DOI":"10.1109\/RFIC.2004.1320575"},{"issue":"12","key":"9_CR26","doi-asserted-by":"crossref","first-page":"2278","DOI":"10.1109\/JSSC.2004.836345","volume":"39","author":"R Staszewski","year":"2004","unstructured":"R. Staszewski, K. Muhammad, D. Leipold, C.M. Hung, Y.C. Ho, J. Wallberg, C. Fernando, K. Maggio, R. Staszewski, T. Jung, J. Koh, S. John, I.Y. Deng, V. Sarda, O. Moreira-Tamayo, V. Mayega, R. Katz, O. Friedman, O. Eliezer, E. de Obaldia, P. Balsara, All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS. IEEE J. Solid State Circuits 39(12), 2278\u20132291 (2004)","journal-title":"IEEE J. Solid State Circuits"},{"issue":"12","key":"9_CR27","doi-asserted-by":"crossref","first-page":"2469","DOI":"10.1109\/JSSC.2005.857417","volume":"40","author":"R Staszewski","year":"2005","unstructured":"R. Staszewski, J. Wallberg, S. Rezeq, C.M. Hung, O. Eliezer, S. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.C. Lee, P. Cruise, M. Entezari, K. Muhammad, D. Leipold, All-digital PLL and transmitter for mobile phones. IEEE J. Solid State Circuits 40(12), 2469\u20132482 (2005)","journal-title":"IEEE J. Solid State Circuits"},{"issue":"10","key":"9_CR28","doi-asserted-by":"crossref","first-page":"2312","DOI":"10.1109\/JSSC.2011.2162186","volume":"46","author":"Y Tousi","year":"2011","unstructured":"Y. Tousi, E. Afshari, A miniature 2 mW 4 bit 1.2 GS\/s delay-line-based ADC in 65 nm CMOS. IEEE J Solid State Circuits 46(10), 2312\u20132325 (2011)","journal-title":"IEEE J Solid State Circuits"},{"key":"9_CR29","doi-asserted-by":"crossref","unstructured":"K. Townsend, A. Macpherson, J. Haslett, A fine-resolution time-to-digital converter for a 5GS\/S ADC. In IEEE International Circuits and Systems Symposium (Paris, 2010), pp. 3024\u20133027","DOI":"10.1109\/ISCAS.2010.5538004"},{"issue":"3","key":"9_CR30","doi-asserted-by":"crossref","first-page":"237","DOI":"10.1109\/TIM.1986.6499202","volume":"IM\u201335","author":"F Trofimenkoff","year":"1986","unstructured":"F. Trofimenkoff, J. Haslett, A. Nordquist, VFC with pulsewidth-to-period ratio proportional to input voltage. IEEE Trans. Instrum. Meas. IM\u201335(3), 237\u2013244 (1986)","journal-title":"IEEE Trans. Instrum. Meas."},{"key":"9_CR31","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4757-5003-4","volume-title":"Distortion Analysis of Analog Integrated Circuits","author":"P Wambacq","year":"1998","unstructured":"P. Wambacq, W. Sansen, Distortion Analysis of Analog Integrated Circuits (Kluwer Academic Publishers, Norwell, MA, USA, 1998)"},{"issue":"1","key":"9_CR32","doi-asserted-by":"crossref","first-page":"120","DOI":"10.1109\/JSSC.2002.806263","volume":"38","author":"T Watanabe","year":"2003","unstructured":"T. Watanabe, T. Mizuno, Y. Makino, An all-digital analog-to-digital converter with 12- $$\\mu $$ \u03bc V\/LSB using moving-average filtering. IEEE J. Solid State Circuits 38(1), 120\u2013125 (2003)","journal-title":"IEEE J. Solid State Circuits"},{"issue":"5","key":"9_CR33","doi-asserted-by":"crossref","first-page":"1081","DOI":"10.1109\/JSSC.2014.2301764","volume":"49","author":"W Wu","year":"2014","unstructured":"W. Wu, R. Staszewski, J. Long, A 56.4-to-63.4 GHz multi-rate all-digital fractional-N PLL for FMCW radar applications in 65 nm CMOS. IEEE J Solid State Circuits 49(5), 1081\u20131096 (2014)","journal-title":"IEEE J Solid State Circuits"},{"issue":"11","key":"9_CR34","doi-asserted-by":"crossref","first-page":"2481","DOI":"10.1109\/TCSI.2012.2189055","volume":"59","author":"L Xu","year":"2012","unstructured":"L. Xu, K. Stadius, J. Ryynanen, An all-digital PLL frequency synthesizer with an improved phase digitization approach and an optimized frequency calibration technique. IEEE Trans Circuits Syst. I Regul. Pap. 59(11), 2481\u20132494 (2012)","journal-title":"IEEE Trans Circuits Syst. I Regul. Pap."},{"issue":"11","key":"9_CR35","doi-asserted-by":"crossref","first-page":"2316","DOI":"10.1109\/TVLSI.2013.2291563","volume":"22","author":"Y Xu","year":"2014","unstructured":"Y. Xu, L. Belostotski, J. Haslett, A 65-nm CMOS 10-GS\/s 4-bit background-calibrated noninterleaved flash ADC for radio astronomy. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(11), 2316\u20132325 (2014)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"9_CR36","doi-asserted-by":"crossref","unstructured":"T. Yamaguchi, S. Komatsu, M. Abbas, K. Asada, N.N. Mai-Khanh, J. Tandon, A CMOS flash TDC with 0.84-1.3 ps resolution using standard cells. In IEEE Radio Frequency Integrated Circuits Symposium (Montreal, 2012), pp. 527\u2013530","DOI":"10.1109\/RFIC.2012.6242338"},{"issue":"8","key":"9_CR37","doi-asserted-by":"crossref","first-page":"1590","DOI":"10.1109\/JSSC.2005.852042","volume":"40","author":"H Yang","year":"2005","unstructured":"H. Yang, R. Sarpeshkar, A time-based energy-efficient analog-to-digital converter. IEEE J. Solid State Circuits 40(8), 1590\u20131601 (2005)","journal-title":"IEEE J. Solid State Circuits"},{"issue":"5","key":"9_CR38","doi-asserted-by":"crossref","first-page":"1574","DOI":"10.1109\/TNS.2007.903183","volume":"54","author":"A Yousif","year":"2007","unstructured":"A. Yousif, J. Haslett, A fine resolution TDC architecture for next generation PET imaging. IEEE Trans. Nucl. Sci. 54(5), 1574\u20131582 (2007)","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"9_CR39","doi-asserted-by":"crossref","unstructured":"E. Zailer, T. Graham, L. Belostotski, R. Plume, R. Taylor, Analysis of the ADC resolution for radio astronomy applications. In IEEE International Symposium on Antenna Technology and Applied Electromagnetics (Victoria, Canada, 2014), pp. 1\u20134","DOI":"10.1109\/ANTEM.2014.6887738"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-015-0009-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s00034-015-0009-5\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-015-0009-5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,20]],"date-time":"2025-05-20T18:10:07Z","timestamp":1747764607000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s00034-015-0009-5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,3,5]]},"references-count":39,"journal-issue":{"issue":"10","published-print":{"date-parts":[[2015,10]]}},"alternative-id":["9"],"URL":"https:\/\/doi.org\/10.1007\/s00034-015-0009-5","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"type":"print","value":"0278-081X"},{"type":"electronic","value":"1531-5878"}],"subject":[],"published":{"date-parts":[[2015,3,5]]}}}