{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,4]],"date-time":"2022-04-04T13:39:25Z","timestamp":1649079565570},"reference-count":31,"publisher":"Springer Science and Business Media LLC","issue":"10","license":[{"start":{"date-parts":[[2015,3,5]],"date-time":"2015-03-05T00:00:00Z","timestamp":1425513600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2015,10]]},"DOI":"10.1007\/s00034-015-0010-z","type":"journal-article","created":{"date-parts":[[2015,3,4]],"date-time":"2015-03-04T04:09:39Z","timestamp":1425442179000},"page":"3353-3372","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Post-layout Redundant Via Insertion Approach Considering Multiple Via Configuration"],"prefix":"10.1007","volume":"34","author":[{"given":"Tsang-Chi","family":"Kan","sequence":"first","affiliation":[]},{"given":"Shanq-Jang","family":"Ruan","sequence":"additional","affiliation":[]},{"given":"Ting-Feng","family":"Chang","sequence":"additional","affiliation":[]},{"given":"Shih-Hsien","family":"Yang","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2015,3,5]]},"reference":[{"key":"10_CR1","doi-asserted-by":"crossref","unstructured":"R. Aitken, Dfm metrics for standard cells, in IEEE International Symposium on Quality Electronic Design (ISQED) (2006), pp. 490\u2013496","DOI":"10.1109\/ISQED.2006.50"},{"key":"10_CR2","doi-asserted-by":"crossref","unstructured":"Y. Ban, C. Choi, H. Shin, Y. Kang, W.H. Paik, Analysis and optimization of process-induced electromigration on signal interconnects in 16nm FinFET SoC (system-on-chip), in SPIE Advanced Lithography, Design-Process-Technology Co-optimization for Manufacturability VIII (2014), p. 90530P","DOI":"10.1117\/12.2046207"},{"key":"10_CR3","doi-asserted-by":"crossref","unstructured":"Y. Ban, J. Sweis, P. Hurat, Y.C. Lai, Y. Kang, W.H. Paik, W. Xu, H. Song, Layout Induced Variability and Manufacturability Checks in FinFETs Process, in SPIE Advanced Lithography, Design-Process-Technology Co-optimization for Manufacturability VIII (2014), p. 90530I","DOI":"10.1117\/12.2046284"},{"key":"10_CR4","unstructured":"T.F. Chang, T.C. Kan, S.H. Yang, S.J. Ruan, Enhanced redundant via insertion with multi-via mechanisms, in IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2011), pp. 218\u2013223"},{"key":"10_CR5","doi-asserted-by":"crossref","unstructured":"H.Y. Chen, M.F. Chiang, Y.W. Chang, L. Chen, B. Han, Full-chip routing considering double-via insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 844\u2013857 (2008)","DOI":"10.1109\/TCAD.2008.917597"},{"key":"10_CR6","doi-asserted-by":"crossref","unstructured":"H.A. Chien, T.C. Wang, Redundant-via-aware ECO routing, in Proceedings of the ASP-DAC (2014), pp. 418\u2013423","DOI":"10.1109\/ASPDAC.2014.6742927"},{"key":"10_CR7","volume-title":"Introduction to Algorithms","author":"TH Cormem","year":"2009","unstructured":"T.H. Cormem, C.E. Leiserson, R.L. Rivest, C. Stein, Introduction to Algorithms (The MIT Press, Cambridge, 2009)"},{"key":"10_CR8","unstructured":"T. Fujimaki, K. Higashi, N. Nakamura, N. Matsunaga, K. Yoshida, N. Miyawaki, M. Hatano, M. Hasunuma, J. Wada, T. Nishioka, K. Akiyama, H. Kawashima, Y. Enomoto, T. Hasegawa, K. Honda, M. Iwai, S. Yamada, F. Matsuoka, Mechanism of moisture uptake induced via failure and its impact on 45nm node interconnect design, in IEEE International Electron Devices Meeting, (2005), pp. 183\u2013186"},{"key":"10_CR9","doi-asserted-by":"crossref","unstructured":"C. Guardiani, N. Dragone, P. McNamara, Proactive design for manufacturing (dfm) for nanometer soc designs, in Proceedings of the IEEE Custom Integrated Circuits Conference, (2004), pp. 309\u2013316","DOI":"10.1109\/CICC.2004.1358808"},{"key":"10_CR10","unstructured":"W. Guo, S. Chen, M.F. Chiang, J.W. Shen, T. Yoshimura, Convex-cost flow based redundant-via insertion with density-balance consideration, in ASICON, IEEE 8th International Conference on ASIC, (2009), pp. 1280\u20131283"},{"key":"10_CR11","unstructured":"H. Heineken, J. Khare, M. dAbreu, Manufacturability analysis of standard cell libraries, in Proceedings of the IEEE (1998), pp. 321\u2013324"},{"key":"10_CR12","doi-asserted-by":"crossref","unstructured":"X. Hong, Y. Cai, H. Yao, D. Li, Dfm-aware routing for yield enhancement, in Proceedings Asia Pacific Conference on APCCAS, (2006), pp. 1091\u20131094","DOI":"10.1109\/APCCAS.2006.342311"},{"key":"10_CR13","unstructured":"IC Compiler, Synopsys, Mountain View, California (2010)"},{"key":"10_CR14","unstructured":"T.C. Kan, H.M. Hong, Y.J. Chen, S.J. Ruan, Configurable redundant via-aware standard cell design considering multi-via mechanism, in IEEE Internation Symposium on Quality Electronic Design (ISQED) (2013), pp. 322\u2013326"},{"key":"10_CR15","unstructured":"T.C. Kan, S.H. Yang, T.F. Chang, S.J. Ruan, Design of a practical nanometer-scale redundant via-aware standard cell library for improved redundant via1 insertion rate, in IEEE Trans. Very Large Scale Integration (VLSI) Systems (2013), pp. 142\u2013147"},{"key":"10_CR16","doi-asserted-by":"crossref","unstructured":"K.Y. Lee, S.T. Lin, T.C. Wang, Enhanced double via insertion using wire bending. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 171\u2013184 (2010)","DOI":"10.1109\/TCAD.2009.2035559"},{"key":"10_CR17","doi-asserted-by":"crossref","unstructured":"S.T. Lin, K.Y. Lee, T.C. Wang, C.K. Koh, K.Y. Chao, Simultaneous redundant via insertion and line end extension for yield optimization, in 16th Asia and South Pacific Design Automation Conference (ASP-DAC) (2011), pp. 633\u2013638","DOI":"10.1109\/ASPDAC.2011.5722266"},{"key":"10_CR18","unstructured":"C.T. Lin, Y.H. Lin, G.C. Su, Y. L. Li, Dead via minimization by simultaneous routing and redundant via insertion, in Design Automation Conference (ASP-DAC), 15th Asia and South Pacific (2010), pp. 657\u2013662"},{"key":"10_CR19","doi-asserted-by":"crossref","unstructured":"T.Y. Lin, T.H. Lin, H.H. Tung, R.B. Lin, Double-via-driven standard cell library design, in Design, Automation Test in Europe Conference Exhibition (DATE) (2007), pp. 1\u20136","DOI":"10.1109\/DATE.2007.364460"},{"key":"10_CR20","doi-asserted-by":"crossref","unstructured":"F. Luo, Y. Jia, W.W.M. Dai, Yield-preferred via insertion based on novel geotopological technology, in Asia and South Pacific Conference on Design Automation (2006), p. 6","DOI":"10.1145\/1118299.1118469"},{"key":"10_CR21","doi-asserted-by":"crossref","unstructured":"K. McCullen, Redundant via insertion in restricted topology layouts, in IEEE International Symposium on Quality Electronic Design (ISQED) (2007), pp. 821\u2013828","DOI":"10.1109\/ISQED.2007.138"},{"key":"10_CR22","doi-asserted-by":"crossref","unstructured":"C.W. Pan, Y. M. Lee, Redundant via insertion under timing constraints, in 12th International Symposium on Quality Electronic Design (ISQED) (2011), pp. 1\u20137","DOI":"10.1109\/ISQED.2011.5770794"},{"key":"10_CR23","unstructured":"D. Pan, M. Wong, Manufacturability-aware physical layout optimizations, in ICICDT, International Conference on Integrated Circuit Design and Technology, (2005), pp. 149\u2013153"},{"key":"10_CR24","unstructured":"J.W. Shen, C.M. Fang, S. Chen, W. Guo, T. Yoshimura, Redundant via allocation for layer partition-based redundant via insertion, in IEEE 8th International Conference on ASIC (ASICON 09) (2009), pp. 734\u2013737"},{"key":"10_CR25","unstructured":"H. Sunagawa, H. Terada, A. Tsuchiya, K. Kobayashi, H. Onodera, in Effect of regularity-enhanced layout on variability and circuit performance of standard cells, vol 3 (2010), pp. 130\u2013139"},{"key":"10_CR26","doi-asserted-by":"crossref","unstructured":"C.C. Tsai, C.C. Kuo, L.J. Gu, T.Y. Lee, Double-via insertion enhanced x-architecture clock routing for reliability, in IEEE International Symposium on Circuits and Systems (ISCAS) (2010), pp. 3413\u20133416","DOI":"10.1109\/ISCAS.2010.5537863"},{"key":"10_CR27","unstructured":"J.G. Xi, Improving Yield in RTL-to-GDSII Flows, EE Times. 11 July 2005"},{"key":"10_CR28","doi-asserted-by":"crossref","unstructured":"G. Xu, L. Huang, D. Pan, M. Wong, Redundant-via enhanced maze routing for yield improvement, in Proceedings of the ASP-DAC, (2005), pp. 1148\u20131151","DOI":"10.1145\/1120725.1120927"},{"key":"10_CR29","doi-asserted-by":"crossref","unstructured":"J.T. Yan, B.Y. Chiang, Z.W. Chen, Yield-driven redundant via insertion based on probabilistic via-connection analysis, in IEEE International Conference on Electronics, Circuits and Systems, (2006), pp. 874\u2013877","DOI":"10.1109\/ICECS.2006.379928"},{"key":"10_CR30","doi-asserted-by":"crossref","unstructured":"H. Yao, Y. Cai, Q. Zhou, X. Hong, Multilevel routing with redundant via insertion. IEEE Trans. Circuits Syst. II Express Briefs 1148\u20131152, (2006)","DOI":"10.1109\/TCSII.2006.881822"},{"key":"10_CR31","doi-asserted-by":"crossref","unstructured":"Y. Zorian, Optimizing manufacturability by design for yield, in IEEE\/CPMT\/SEMI Electronics Manufacturing Technology Symposium (2004), pp. 255\u2013258","DOI":"10.1109\/IEMT.2004.1321672"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-015-0010-z.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s00034-015-0010-z\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-015-0010-z","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,21]],"date-time":"2019-08-21T12:41:32Z","timestamp":1566391292000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s00034-015-0010-z"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,3,5]]},"references-count":31,"journal-issue":{"issue":"10","published-print":{"date-parts":[[2015,10]]}},"alternative-id":["10"],"URL":"https:\/\/doi.org\/10.1007\/s00034-015-0010-z","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"value":"0278-081X","type":"print"},{"value":"1531-5878","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,3,5]]}}}