{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T14:34:39Z","timestamp":1753886079933,"version":"3.41.0"},"reference-count":15,"publisher":"Springer Science and Business Media LLC","issue":"9","license":[{"start":{"date-parts":[[2017,1,3]],"date-time":"2017-01-03T00:00:00Z","timestamp":1483401600000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2017,9]]},"DOI":"10.1007\/s00034-016-0481-6","type":"journal-article","created":{"date-parts":[[2017,1,3]],"date-time":"2017-01-03T12:30:13Z","timestamp":1483446613000},"page":"3514-3526","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":10,"title":["A Novel Charge Pump with Low Current for Low-Power Delay-Locked Loops"],"prefix":"10.1007","volume":"36","author":[{"given":"Motahhareh","family":"Estebsari","sequence":"first","affiliation":[]},{"given":"Mohammad","family":"Gholami","sequence":"additional","affiliation":[]},{"given":"Mohammad Javad","family":"Ghahramanpour","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2017,1,3]]},"reference":[{"key":"481_CR1","unstructured":"C.C. Chung, C.L. Chang, A wide-range all-digital delay-locked loop in 65nm CMOS technology. In 2010 International Symposium on VLSI Design Automation and Test (VLSI-DAT), Apr 26. IEEE (2010), pp. 66\u201369"},{"key":"481_CR2","unstructured":"M. Estebsari, M. Gholami, M.J. Ghahramanpour, A wide frequency range delay line for fast-locking and low power delay-locked-loops. Analog Integrated Circuits and Signal Processing (2016), pp. 1\u20138"},{"issue":"2","key":"481_CR3","doi-asserted-by":"crossref","first-page":"781","DOI":"10.1007\/s00034-012-9488-9","volume":"32","author":"M Gholami","year":"2013","unstructured":"M. Gholami, A novel low power architecture for DLL-based frequency synthesizers. Circuits Syst. Signal Process. 32(2), 781\u2013801 (2013)","journal-title":"Circuits Syst. Signal Process."},{"issue":"6","key":"481_CR4","first-page":"2040","volume":"24","author":"M Gholami","year":"2016","unstructured":"M. Gholami, Total jitter of delay-locked loops due to four main jitter sources. IEEE Trans. Very Large Scale Integr. Syst. 24(6), 2040\u20132049 (2016)","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"issue":"5","key":"481_CR5","doi-asserted-by":"crossref","first-page":"566","DOI":"10.1002\/cta.1958","volume":"43","author":"M Gholami","year":"2015","unstructured":"M. Gholami, H. Rahimpour, G. Ardeshir, H. Miar-Naimi, A new fast-lock, low-jitter, and all-digital frequency synthesizer for DVB-T receivers. Int. J. Cir. Theory Appl. 43(5), 566\u2013578 (2015)","journal-title":"Int. J. Cir. Theory Appl."},{"issue":"12","key":"481_CR6","first-page":"1988","volume":"28","author":"X Hong","year":"2007","unstructured":"X. Hong, L. Zhiqun, W. Zhigong, L. Wei, Z. Li, A charge pump design for low-spur PLL. Chin. J. Semicond. Chin. Ed. 28(12), 1988 (2007)","journal-title":"Chin. J. Semicond. Chin. Ed."},{"issue":"23","key":"481_CR7","doi-asserted-by":"crossref","first-page":"1436","DOI":"10.1049\/el.2013.1304","volume":"49","author":"M Jalalifar","year":"2013","unstructured":"M. Jalalifar, G.S. Byun, Near-threshold charge pump circuit using dual feedback loop. Electron. Lett. 49(23), 1436\u20131438 (2013)","journal-title":"Electron. Lett."},{"key":"481_CR8","unstructured":"C. Jia, A Delay-Locked Loop for Multiple Clock Phases\/Delays Generation PhD report, Georgia Institute of Technology, December (2005)"},{"issue":"9","key":"481_CR9","doi-asserted-by":"crossref","first-page":"661","DOI":"10.1049\/el.2014.0804","volume":"50","author":"N Joram","year":"2014","unstructured":"N. Joram, R. Wolf, F. Ellinger, High swing PLL charge pump with current mismatch reduction. Electron. Lett. 50(9), 661\u2013663 (2014)","journal-title":"Electron. Lett."},{"issue":"23","key":"481_CR10","doi-asserted-by":"crossref","first-page":"1907","DOI":"10.1049\/el:20001358","volume":"36","author":"JS Lee","year":"2000","unstructured":"J.S. Lee, M.S. Keel, S.I. Lim, S. Kim, Charge pump with perfect current matching characteristics in phase-locked loops. Electron. Lett. 36(23), 1907\u20131908 (2000)","journal-title":"Electron. Lett."},{"issue":"1","key":"481_CR11","doi-asserted-by":"crossref","first-page":"16","DOI":"10.1049\/el.2011.2835","volume":"48","author":"P Liu","year":"2012","unstructured":"P. Liu, P. Sun, J. Jung, D. Heo, PLL charge pump with adaptive body-bias compensation for minimum current variation. Electron. Lett. 48(1), 16\u201318 (2012)","journal-title":"Electron. Lett."},{"key":"481_CR12","doi-asserted-by":"crossref","unstructured":"W. Rhee, Design of high-performance CMOS charge pumps in phase-locked loops. In Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, 1999. ISCAS\u201999. IEEE, Jul Vol. 2 (1999), pp. 545\u2013548)","DOI":"10.1109\/ISCAS.1999.780807"},{"key":"481_CR13","doi-asserted-by":"crossref","unstructured":"Y. Sun, L. Siek, P. Song, Design of a high performance charge pump circuit for low voltage phase-locked loops. In 2007 International Symposium on Integrated Circuits 2007 Sep 26. IEEE (2007), pp. 271\u2013274","DOI":"10.1109\/ISICIR.2007.4441850"},{"issue":"4","key":"481_CR14","doi-asserted-by":"crossref","first-page":"896","DOI":"10.1109\/TCSI.2012.2215393","volume":"60","author":"T Yoshimura","year":"2013","unstructured":"T. Yoshimura, S. Iwade, H. Makino, Y. Matsuda, Analysis of pull-in range limit by charge pump mismatch in a linear phase-locked loop. IEEE Trans. Circuits Syst. I Regul. Pap. 60(4), 896\u2013907 (2013)","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"481_CR15","doi-asserted-by":"crossref","unstructured":"S. Zheng, Z. Li, A novel CMOS charge pump with high performance for phase-locked loops synthesizer. In 2011 IEEE 13th International Conference on Communication Technology (ICCT). IEEE (2011 Sep 25), pp. 1062\u20131065","DOI":"10.1109\/ICCT.2011.6158043"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s00034-016-0481-6\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-016-0481-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-016-0481-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,13]],"date-time":"2025-06-13T23:57:59Z","timestamp":1749859079000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s00034-016-0481-6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,1,3]]},"references-count":15,"journal-issue":{"issue":"9","published-print":{"date-parts":[[2017,9]]}},"alternative-id":["481"],"URL":"https:\/\/doi.org\/10.1007\/s00034-016-0481-6","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"type":"print","value":"0278-081X"},{"type":"electronic","value":"1531-5878"}],"subject":[],"published":{"date-parts":[[2017,1,3]]}}}