{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T11:03:07Z","timestamp":1740135787488,"version":"3.37.3"},"reference-count":16,"publisher":"Springer Science and Business Media LLC","issue":"12","license":[{"start":{"date-parts":[[2017,9,19]],"date-time":"2017-09-19T00:00:00Z","timestamp":1505779200000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2017,12]]},"DOI":"10.1007\/s00034-017-0664-9","type":"journal-article","created":{"date-parts":[[2017,9,19]],"date-time":"2017-09-19T07:36:36Z","timestamp":1505806596000},"page":"4994-5018","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Analysis and Design of Single Reference Reduced Summer Loading-Based Switched Capacitor DFE"],"prefix":"10.1007","volume":"36","author":[{"given":"Nevin Alex","family":"Jacob","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3563-9096","authenticated-orcid":false,"given":"Bibhudatta","family":"Sahoo","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2017,9,19]]},"reference":[{"issue":"12","key":"664_CR1","doi-asserted-by":"crossref","first-page":"2633","DOI":"10.1109\/JSSC.2005.856584","volume":"40","author":"T Beukema","year":"2005","unstructured":"T. Beukema et al., A 6.4 Gb\/s CMOS serdes core with feed forward and decision-feedback equalization. IEEE J. Solid State Circuits 40(12), 2633\u20132645 (2005)","journal-title":"IEEE J. Solid State Circuits"},{"issue":"12","key":"664_CR2","doi-asserted-by":"crossref","first-page":"3232","DOI":"10.1109\/JSSC.2012.2216414","volume":"47","author":"JF Bulzacchelli","year":"2012","unstructured":"J.F. Bulzacchelli et al., A 28-Gb\/s 4-tap FFE\/15-tap DFE serial link transceiver in 32 nm SOI CMOS technology. IEEE J. Solid State Circuits 47(12), 3232\u20133248 (2012)","journal-title":"IEEE J. Solid State Circuits"},{"key":"664_CR3","unstructured":"O. Elhadidy, S. Palermo, A 10 Gb\/s 2-IIR-Tap DFE Receiver with 35 dB Loss Compensation in 65-nm CMOS, in VLSI Symposium, (2013), pp. C272\u2013C273"},{"issue":"4","key":"664_CR4","doi-asserted-by":"crossref","first-page":"889","DOI":"10.1109\/JSSC.2007.892156","volume":"42","author":"A Emami-Neyestanak","year":"2007","unstructured":"A. Emami-Neyestanak et al., A 6.0 mW 10.0-Gb\/s receiver with switched capacitor summation DFE. IEEE J. Solid State Circuits 42(4), 889\u2013896 (2007)","journal-title":"IEEE J. Solid State Circuits"},{"key":"664_CR5","unstructured":"Y.-C. Huang, S.-I. Liu, A 6 Gb\/s receiver with 32.7 dB Adaptive DFE-IIR Equalization, in IEEE International Solid-State Circuits Conference, (2011), pp. 356\u2013358"},{"issue":"12","key":"664_CR6","doi-asserted-by":"crossref","first-page":"3526","DOI":"10.1109\/JSSC.2009.2031015","volume":"44","author":"B Kim","year":"2009","unstructured":"B. Kim et al., A 10-Gb\/s compact low-power serial I\/O with DFE-IIR equalization in 65-nm CMOS. IEEE J. Solid State Circuits 44(12), 3526\u20133538 (2009)","journal-title":"IEEE J. Solid State Circuits"},{"issue":"10","key":"664_CR7","doi-asserted-by":"crossref","first-page":"2420","DOI":"10.1109\/JSSC.2012.2203870","volume":"47","author":"MH Nazari","year":"2012","unstructured":"M.H. Nazari, A. Emami-Neyestanak, A 15-Gb\/s 0.5-mW\/Gbps two tap DFE receiver with far-end crosstalk cancellation. IEEE J. Solid State Circuits 47(10), 2420\u20132432 (2012)","journal-title":"IEEE J. Solid State Circuits"},{"key":"664_CR8","unstructured":"J. Nevin Alex et al., Full-rate Switched Capacitor Multi-tap DFE for Long-Tail Post-cursor Cancellation, in 59th International Midwest Symposium on Circuits and Systems (MWSCAS) (2016)"},{"key":"664_CR9","unstructured":"M. Park et al., A 7 Gb\/s 9.3 mW 2-Tap Current-Integrating DFE Receiver, in IEEE International Solid-State Circuits Conference, (2007), pp. 230\u2013599"},{"key":"664_CR10","unstructured":"P.\u00a0Patel, Experimental Backplane Test Fixture (2011) (Online). \n                        http:\/\/www.ieee802.org\/3\/100GCU\/public\/channel.html"},{"key":"664_CR11","unstructured":"W. Peters, IEEE P802.3ap Task Force Channel Model Material (2005) (Online). \n                        http:\/\/www.ieee802.org\/3\/ap\/public\/channel_model"},{"key":"664_CR12","doi-asserted-by":"crossref","unstructured":"B. Razavi, Charge steering: a low-power design paradigm, in Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San Jose, CA, 2013, pp. 1\u20138","DOI":"10.1109\/CICC.2013.6658443"},{"issue":"6","key":"664_CR13","doi-asserted-by":"crossref","first-page":"326","DOI":"10.1109\/TCSII.2012.2195055","volume":"59","author":"S Shahramian","year":"2012","unstructured":"S. Shahramian et al., Decision feedback equalizer architectures with multiple continuous-time infinite impulse response filters. IEEE Trans. Circuit Syst II 59(6), 326\u2013330 (2012)","journal-title":"IEEE Trans. Circuit Syst II"},{"issue":"4","key":"664_CR14","doi-asserted-by":"crossref","first-page":"1012","DOI":"10.1109\/JSSC.2004.842863","volume":"40","author":"V Stojanovic","year":"2005","unstructured":"V. Stojanovic et al., Autonomous dual-mode (PAM2\/4) serial link transceiver with adaptive equalization and data recovery. IEEE J. Solid State Circuits 40(4), 1012\u20131026 (2005)","journal-title":"IEEE J. Solid State Circuits"},{"key":"664_CR15","unstructured":"C.\u00a0Thakkar, E.\u00a0Alon, Design of Multi-Gb\/s Multi-Coefficient Mixed-Signal Equalizers, Technical Report No. UCB\/EECS-2014-189 (2014)"},{"issue":"4","key":"664_CR16","doi-asserted-by":"crossref","first-page":"897","DOI":"10.1109\/JSSC.2012.2185342","volume":"47","author":"T Toifl","year":"2012","unstructured":"T. Toifl et al., A 2.6mW\/Gbps 12.5 Gbps RX with 8-tap switched capacitor DFE in 32nm CMOS. IEEE J. Solid State Circuits 47(4), 897\u2013910 (2012)","journal-title":"IEEE J. Solid State Circuits"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s00034-017-0664-9\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-017-0664-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-017-0664-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,9,27]],"date-time":"2017-09-27T03:38:43Z","timestamp":1506483523000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s00034-017-0664-9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,9,19]]},"references-count":16,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2017,12]]}},"alternative-id":["664"],"URL":"https:\/\/doi.org\/10.1007\/s00034-017-0664-9","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"type":"print","value":"0278-081X"},{"type":"electronic","value":"1531-5878"}],"subject":[],"published":{"date-parts":[[2017,9,19]]}}}