{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,4]],"date-time":"2025-07-04T15:40:06Z","timestamp":1751643606527,"version":"3.41.0"},"reference-count":32,"publisher":"Springer Science and Business Media LLC","issue":"12","license":[{"start":{"date-parts":[[2018,5,15]],"date-time":"2018-05-15T00:00:00Z","timestamp":1526342400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2018,12]]},"DOI":"10.1007\/s00034-018-0837-1","type":"journal-article","created":{"date-parts":[[2018,5,15]],"date-time":"2018-05-15T12:52:54Z","timestamp":1526388774000},"page":"5595-5615","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Reliable VLSI Architecture Design Using Modulo-Quad-Transistor Redundancy Method"],"prefix":"10.1007","volume":"37","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5887-3563","authenticated-orcid":false,"given":"Atin","family":"Mukherjee","sequence":"first","affiliation":[]},{"given":"Anindya Sundar","family":"Dhar","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2018,5,15]]},"reference":[{"key":"837_CR1","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"422","DOI":"10.1007\/978-3-540-73007-1_52","volume-title":"Computational and Ambient Intelligence","author":"L Anghel","year":"2007","unstructured":"L. Anghel, M. Nicolaidis, Defects tolerant logic gates for unreliable future nanotechnologies, in Computational and Ambient Intelligence, vol. 4507, Lecture Notes in Computer Science, ed. by F. Sandoval, A. Prieto, J. Cabestany, M. Gra\u00f1a (Springer, Berlin, 2007), pp. 422\u2013429"},{"key":"837_CR2","unstructured":"D. Bryan, The ISCAS\u201985 benchmark circuits and netlist format. Technischer Bericht, Microelectronics Center of North Carolina (1988)"},{"key":"837_CR3","doi-asserted-by":"crossref","unstructured":"H. Chen, J. Han, F. Lombardi, A transistor-level stochastic approach for evaluating the reliability of digital nanometric CMOS circuits, in Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, pp. 60\u201367 (2011)","DOI":"10.1109\/DFT.2011.23"},{"issue":"4","key":"837_CR4","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/2602156","volume":"10","author":"J Chen","year":"2014","unstructured":"J. Chen, G. Venkataramani, H.H. Huang, Exploring dynamic redundancy to resuscitate faulty PCM blocks. ACM J. Emerg. Technol. Comput. Syst. 10(4), 1\u201323 (2014)","journal-title":"ACM J. Emerg. Technol. Comput. Syst."},{"key":"837_CR5","doi-asserted-by":"crossref","unstructured":"Y. Cui, W. Li, X. Zhang, Memory controller design based on quadruple modular redundant architecture, in Proceedings International Conference on Computer Engineering and Networks, pp. 905\u2013912 (2013)","DOI":"10.1007\/978-3-319-01766-2_103"},{"issue":"3","key":"837_CR6","doi-asserted-by":"publisher","first-page":"935","DOI":"10.1109\/TR.2015.2440234","volume":"64","author":"AH El-Maleh","year":"2015","unstructured":"A.H. El-Maleh, K. Daud, Simulation-based method for synthesizing soft error tolerant combinational circuits. IEEE Trans. Reliab. 64(3), 935\u2013948 (2015)","journal-title":"IEEE Trans. Reliab."},{"key":"837_CR7","series-title":"Lecture Notes in Electrical Engineering","doi-asserted-by":"publisher","first-page":"29","DOI":"10.1007\/978-90-481-8540-5_3","volume-title":"Robust Computing with Nano-scale Devices","author":"AH El-Maleh","year":"2010","unstructured":"A.H. El-Maleh, B.M. Al-Hashimi, A. Melouki, A. Al-Yamani, Transistor-level based defect-tolerance for reliable nanoelectronics, in Robust Computing with Nano-scale Devices, Lecture Notes in Electrical Engineering, ed. by C. Huang (Springer, Dordrecht, 2010), pp. 29\u201349"},{"issue":"6","key":"837_CR8","doi-asserted-by":"publisher","first-page":"1336","DOI":"10.1109\/TC.2012.276","volume":"63","author":"J Han","year":"2014","unstructured":"J. Han, H. Chen, J. Liang, P. Zhu, Z. Yang, F. Lombardi, A stochastic computational approach for accurate and efficient reliability evaluation. IEEE Trans. Comput. 63(6), 1336\u20131350 (2014)","journal-title":"IEEE Trans. Comput."},{"issue":"8","key":"837_CR9","doi-asserted-by":"publisher","first-page":"1562","DOI":"10.1109\/TVLSI.2014.2341610","volume":"23","author":"J Han","year":"2015","unstructured":"J. Han, E. Leung, L. Leibo, F. Lombardi, A fault-tolerant technique using quadded logic and quadded transistors. IEEE Trans. Very Large Scale Integr. VLSI Syst. 23(8), 1562\u20131566 (2015)","journal-title":"IEEE Trans. Very Large Scale Integr. VLSI Syst."},{"issue":"7","key":"837_CR10","doi-asserted-by":"publisher","first-page":"1076","DOI":"10.1016\/j.jprocont.2014.04.012","volume":"24","author":"E Hatami","year":"2014","unstructured":"E. Hatami, H. Salarieh, N. Vosoughi, Design of a fault tolerated intelligent control system for a nuclear reactor power control: using extended Kalman filter. J. Process Control 24(7), 1076\u20131084 (2014)","journal-title":"J. Process Control"},{"issue":"4","key":"837_CR11","doi-asserted-by":"publisher","first-page":"316","DOI":"10.1109\/MDT.2005.76","volume":"22","author":"C He","year":"2005","unstructured":"C. He, M.F. Jacome, G. de Veciana, A reconfiguration-based defect-tolerant design paradigm for nanotechnologies. IEEE Des. Test. Comput. 22(4), 316\u2013326 (2005)","journal-title":"IEEE Des. Test. Comput."},{"issue":"9","key":"837_CR12","doi-asserted-by":"publisher","first-page":"2433","DOI":"10.1109\/TC.2014.2366743","volume":"64","author":"S Hong","year":"2015","unstructured":"S. Hong, S. Kim, A low-cost mechanism exploiting narrow-width values for tolerating hard faults in ALU. IEEE Trans. Comput. 64(9), 2433\u20132446 (2015)","journal-title":"IEEE Trans. Comput."},{"key":"837_CR13","doi-asserted-by":"crossref","unstructured":"M.M. Ibrahim, K. Asami, M. Cho, Reconfigurable fault tolerant avionics system, in Proceedings IEEE Aerospace Conference, pp. 1\u201312 (2013)","DOI":"10.1109\/AERO.2013.6497203"},{"issue":"3","key":"837_CR14","doi-asserted-by":"publisher","first-page":"22","DOI":"10.1109\/TR.1963.5218213","volume":"12","author":"PA Jensen","year":"1963","unstructured":"P.A. Jensen, Quadded NOR logic. IEEE Trans. Reliab. 12(3), 22\u201331 (1963)","journal-title":"IEEE Trans. Reliab."},{"issue":"4","key":"837_CR15","doi-asserted-by":"publisher","first-page":"328","DOI":"10.1109\/MDT.2005.97","volume":"22","author":"P Jonker","year":"2005","unstructured":"P. Jonker, J.A.B. Fortes, Toward hardware-redundant, fault-tolerant logic for nanoelectronics. IEEE Des. Test. Comput. 22(4), 328\u2013339 (2005)","journal-title":"IEEE Des. Test. Comput."},{"issue":"3","key":"837_CR16","doi-asserted-by":"publisher","first-page":"1536","DOI":"10.1109\/TAES.2013.6558003","volume":"49","author":"M Juliato","year":"2013","unstructured":"M. Juliato, C. Gebotys, A quantitative analysis of a novel SEU-resistant SHA-2 and HMAC architecture for space missions security. IEEE Trans. Aerosp. Electron. Syst. 49(3), 1536\u20131554 (2013)","journal-title":"IEEE Trans. Aerosp. Electron. Syst."},{"key":"837_CR17","unstructured":"F. Khan, Transistor-level defect-tolerant techniques for reliable design: at the nanoscale. Master of Science Thesis, King Fahd University of Petroleum and Minerals (2009)"},{"issue":"3","key":"837_CR18","doi-asserted-by":"publisher","first-page":"323","DOI":"10.1109\/TC.2010.253","volume":"61","author":"EP Kim","year":"2012","unstructured":"E.P. Kim, N.R. Shanbhag, Soft N-modular redundancy. IEEE Trans. Comput. 61(3), 323\u2013336 (2012)","journal-title":"IEEE Trans. Comput."},{"issue":"5","key":"837_CR19","doi-asserted-by":"publisher","first-page":"405","DOI":"10.1007\/s10836-007-5009-3","volume":"23","author":"F Kocan","year":"2007","unstructured":"F. Kocan, D.G. Saab, Dynamic fault diagnosis of combinational and sequential circuits on reconfigurable hardware. J. Electron. Test. 23(5), 405\u2013420 (2007)","journal-title":"J. Electron. Test."},{"key":"837_CR20","doi-asserted-by":"publisher","first-page":"301","DOI":"10.1016\/j.procs.2014.11.066","volume":"42","author":"Z Latifi","year":"2014","unstructured":"Z. Latifi, A. Karimi, A TMR genetic voting algorithm for fault-tolerant medical robot. Proc. Comput. Sci. 42, 301\u2013307 (2014)","journal-title":"Proc. Comput. Sci."},{"issue":"2","key":"837_CR21","doi-asserted-by":"publisher","first-page":"200","DOI":"10.1147\/rd.62.0200","volume":"6","author":"RE Lyions","year":"1962","unstructured":"R.E. Lyions, W. Vanderkulk, The use of triple modular redundancy to improve computer reliability. IBM J. Res. Dev. 6(2), 200\u2013209 (1962)","journal-title":"IBM J. Res. Dev."},{"issue":"3\u20134","key":"837_CR22","doi-asserted-by":"publisher","first-page":"704","DOI":"10.1016\/j.microrel.2014.12.011","volume":"55","author":"A Mukherjee","year":"2015","unstructured":"A. Mukherjee, A.S. Dhar, Real-time fault-tolerance with hot-standby topology for conditional sum adder. Microelectron. Reliab. 55(3\u20134), 704\u2013712 (2015)","journal-title":"Microelectron. Reliab."},{"issue":"3","key":"837_CR23","doi-asserted-by":"publisher","first-page":"152","DOI":"10.1049\/iet-cds.2014.0106","volume":"9","author":"A Mukherjee","year":"2015","unstructured":"A. Mukherjee, A.S. Dhar, Fault tolerant architecture design using quad-gate-transistor redundancy. IET Circuits Dev. Syst. 9(3), 152\u2013160 (2015)","journal-title":"IET Circuits Dev. Syst."},{"key":"837_CR24","doi-asserted-by":"crossref","unstructured":"A. Mukherjee, A.S. Dhar, New triple-transistor based defect-tolerant systems for reliable digital architectures, in Proceedings IEEE Int\u2019l Symposium on Circuits and Systems (ISCAS), pp. 1917\u20131920 (2015)","DOI":"10.1109\/ISCAS.2015.7169047"},{"key":"837_CR25","doi-asserted-by":"crossref","unstructured":"K. Nikolic, A. Sadek, M. Forshaw, Architectures for reliable computing with unreliable nanodevices, in Proceedings IEEE Conference on Nanotechnology, pp. 254\u2013259 (2001)","DOI":"10.1109\/NANO.2001.966429"},{"issue":"1","key":"837_CR26","doi-asserted-by":"publisher","first-page":"55","DOI":"10.1016\/0016-0032(64)90039-0","volume":"277","author":"WH Pierce","year":"1964","unstructured":"W.H. Pierce, Interwoven redundant logic. J. Frankl. Inst. 277(1), 55\u201385 (1964)","journal-title":"J. Frankl. Inst."},{"issue":"1","key":"837_CR27","doi-asserted-by":"publisher","first-page":"93","DOI":"10.1109\/TC.2010.202","volume":"60","author":"W Qian","year":"2011","unstructured":"W. Qian, X. Li, M.D. Riedel, K. Bazargan, D.J. Lilja, An architecture for fault-tolerant computation with stochastic logic. IEEE Trans. Comput. 60(1), 93\u2013105 (2011)","journal-title":"IEEE Trans. Comput."},{"issue":"1","key":"837_CR28","doi-asserted-by":"publisher","first-page":"224","DOI":"10.1109\/TVLSI.2016.2569532","volume":"25","author":"AT Sheikh","year":"2017","unstructured":"A.T. Sheikh, A.H. El-Maleh, M.E.S. Elrabaa, S.M. Sait, A. Fault, Tolerance technique for combinational circuits based on selective-transistor redundancy. IEEE Trans. Very Large Scale Integr. VLSI Syst. 25(1), 224\u2013237 (2017)","journal-title":"IEEE Trans. Very Large Scale Integr. VLSI Syst."},{"key":"837_CR29","unstructured":"J.G. Tryon, Redundant logic circuitry, U. S. Patent 2,942,193, June 21, 1960"},{"key":"837_CR30","first-page":"205","volume-title":"Redundancy Techniques for Computing Systems","author":"JG Tryon","year":"1962","unstructured":"J.G. Tryon, Quadded logic, in Redundancy Techniques for Computing Systems, ed. by R.H. Wilcox, W.C. Mann (Spartan Books, Washington, 1962), pp. 205\u2013208"},{"key":"837_CR31","first-page":"43","volume-title":"Automata Studies: Annals of Mathematics Studies","author":"J Neumann von","year":"1956","unstructured":"J. von Neumann, Probabilistic logic and the synthesis of reliable organisms from unreliable components, in Automata Studies: Annals of Mathematics Studies, vol. 34, ed. by C.E. Shannon, J. McCarthy (Princeton University Press, Princeton, 1956), pp. 43\u201398"},{"key":"837_CR32","first-page":"813","volume":"532\u2013533","author":"H Zhou","year":"2012","unstructured":"H. Zhou, Y.H. Tang, J.F. Jiang, Design and implementation of scalable autonomous centralized fault-tolerant scheme for satellite system. Adv. Mater. Res. 532\u2013533, 813\u2013817 (2012)","journal-title":"Adv. Mater. Res."}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s00034-018-0837-1\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-018-0837-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-018-0837-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,4]],"date-time":"2025-07-04T14:59:27Z","timestamp":1751641167000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s00034-018-0837-1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,5,15]]},"references-count":32,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2018,12]]}},"alternative-id":["837"],"URL":"https:\/\/doi.org\/10.1007\/s00034-018-0837-1","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"type":"print","value":"0278-081X"},{"type":"electronic","value":"1531-5878"}],"subject":[],"published":{"date-parts":[[2018,5,15]]},"assertion":[{"value":"19 August 2017","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"3 May 2018","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"7 May 2018","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"15 May 2018","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}