{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,27]],"date-time":"2026-01-27T23:03:24Z","timestamp":1769555004734,"version":"3.49.0"},"reference-count":14,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2018,5,29]],"date-time":"2018-05-29T00:00:00Z","timestamp":1527552000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2019,1]]},"DOI":"10.1007\/s00034-018-0858-9","type":"journal-article","created":{"date-parts":[[2018,5,28]],"date-time":"2018-05-28T22:47:19Z","timestamp":1527547639000},"page":"287-303","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":26,"title":["Two Novel Ultra-Low-Power SRAM Cells with Separate Read and Write Path"],"prefix":"10.1007","volume":"38","author":[{"given":"Shokoufeh","family":"Naghizadeh","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4696-5900","authenticated-orcid":false,"given":"Mohammad","family":"Gholami","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2018,5,29]]},"reference":[{"key":"858_CR1","unstructured":"Haghdad K, Parametric yield of VLSI systems under variability. Analysis and design solutions, PhD dissertation, Electrical and Computer Engineering, University of Waterloo, (2011)"},{"key":"858_CR2","doi-asserted-by":"publisher","first-page":"385","DOI":"10.1007\/s00034-015-0086-5","volume":"35","author":"CB Kushwah","year":"2016","unstructured":"C.B. Kushwah, S.K. Vishvakarma, D. Dwivedi, Single single-ended boost-less (SE-BL) 7T process tolerant SRAM design in sub-threshold regime for ultra-low-power applications. Circuits Syst. Signal Process. 35, 385\u2013407 (2016)","journal-title":"Circuits Syst. Signal Process."},{"key":"858_CR3","doi-asserted-by":"publisher","unstructured":"K. Mehrabi, B. Ebrahimi, A. Afzali-Kusha, A robust and low power 7T SRAM cell design, in 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS), 2015. \n                    https:\/\/doi.org\/10.1109\/CADS.2015.7377782","DOI":"10.1109\/CADS.2015.7377782"},{"key":"858_CR4","doi-asserted-by":"publisher","first-page":"1437","DOI":"10.1007\/s00034-015-0119-0","volume":"35","author":"M Moghaddam","year":"2016","unstructured":"M. Moghaddam, S. Timarchi, M.H. Moaiyeri, M. Eshghi, An ultra-low-power 9T SRAM cell based on threshold voltage techniques. Circuits Syst. Signal Process. 35, 1437\u20131455 (2016)","journal-title":"Circuits Syst. Signal Process."},{"key":"858_CR5","doi-asserted-by":"publisher","DOI":"10.1007\/978-81-322-1937-8","volume-title":"Low-Power VLSI Circuits and Systems","author":"A Pal","year":"2015","unstructured":"A. Pal, Low-Power VLSI Circuits and Systems (Springer, New Delhi, 2015)"},{"key":"858_CR6","unstructured":"P. Pavan Kumar, R. Reddy, M. Lakshmi, Design of high speed and low power 4T SRAM cell, in International Journal of Scientific and Research Publications. 5, 2015"},{"key":"858_CR7","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-8363-1","volume-title":"CMOS SRAM circuit design and parametric test in nano-scaled technologies","author":"A Pavlov","year":"2008","unstructured":"A. Pavlov, M. Sachdev, CMOS SRAM circuit design and parametric test in nano-scaled technologies (Springer, Dordrecht, 2008)"},{"key":"858_CR8","doi-asserted-by":"publisher","first-page":"289","DOI":"10.1109\/TDMR.2015.2429792","volume":"15","author":"T Pompl","year":"2015","unstructured":"T. Pompl, R. Strasser, S. Drexl, M. Ostermayr, Comprehensive methodology for the statistic of SRAM V\n                           min. IEEE Trans. Device Mater. Reliab. 15, 289\u2013297 (2015)","journal-title":"IEEE Trans. Device Mater. Reliab."},{"key":"858_CR9","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-71713-5","volume-title":"Low Power Design Essentials","author":"J Rabaey","year":"2009","unstructured":"J. Rabaey, Low Power Design Essentials (Springer, Boston, 2009)"},{"key":"858_CR10","doi-asserted-by":"publisher","first-page":"26","DOI":"10.1109\/TCSII.2013.2291064","volume":"61","author":"R Saeidi","year":"2014","unstructured":"R. Saeidi, M. Sharifkhani, K. Hajsadeghi, A subthreshold symmetric SRAM cell with high read stability. IEEE Trans. Circuits Syst. II Express Briefs 61, 26\u201330 (2014)","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"key":"858_CR11","unstructured":"E. Sicard, S. Bendhia, Basics of CMOS Cell Design, (McGraw-Hill Professional, 2007)"},{"key":"858_CR12","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-0818-5","volume-title":"Robust SRAM Designs and Analysis","author":"J Singh","year":"2013","unstructured":"J. Singh, S. Mohanty, D. Pradhan, Robust SRAM Designs and Analysis (Springer, New York, 2013)"},{"key":"858_CR13","doi-asserted-by":"publisher","unstructured":"J. Singh, K. Ramakrishnan, S. Mookerjea, S. Datta, N. Vijaykrishnan, D. Pradhan, A novel Si-tunnel FET based SRAM design for ultra low-power 0.3\u00a0V VDD applications, in 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010. \n                    https:\/\/doi.org\/10.1109\/ASPDAC.2010.5419897","DOI":"10.1109\/ASPDAC.2010.5419897"},{"key":"858_CR14","doi-asserted-by":"publisher","first-page":"2713","DOI":"10.1109\/JSSC.2011.2164009","volume":"46","author":"A Teman","year":"2011","unstructured":"A. Teman, L. Pergament, O. Cohen, A. Fish, A250mV8 kb 40\u00a0nm ultra-lowpower 9T supply feedback SRAM (SF-SRAM). IEEE J. Solid-State Circuits 46, 2713\u20132726 (2011)","journal-title":"IEEE J. Solid-State Circuits"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s00034-018-0858-9\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-018-0858-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-018-0858-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,28]],"date-time":"2019-05-28T20:36:07Z","timestamp":1559075767000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s00034-018-0858-9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,5,29]]},"references-count":14,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2019,1]]}},"alternative-id":["858"],"URL":"https:\/\/doi.org\/10.1007\/s00034-018-0858-9","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"value":"0278-081X","type":"print"},{"value":"1531-5878","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,5,29]]},"assertion":[{"value":"5 January 2018","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"21 May 2018","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"22 May 2018","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"29 May 2018","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}