{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,28]],"date-time":"2026-01-28T21:54:32Z","timestamp":1769637272587,"version":"3.49.0"},"reference-count":33,"publisher":"Springer Science and Business Media LLC","issue":"9","license":[{"start":{"date-parts":[[2019,1,21]],"date-time":"2019-01-21T00:00:00Z","timestamp":1548028800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"funder":[{"DOI":"10.13039\/501100002322","name":"Coordena\u00e7\u00e3o de Aperfei\u00e7oamento de Pessoal de N\u00edvel Superior","doi-asserted-by":"publisher","award":["Finance Code 001"],"award-info":[{"award-number":["Finance Code 001"]}],"id":[{"id":"10.13039\/501100002322","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2019,9]]},"DOI":"10.1007\/s00034-019-01037-w","type":"journal-article","created":{"date-parts":[[2019,1,21]],"date-time":"2019-01-21T06:27:07Z","timestamp":1548052027000},"page":"4014-4039","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":34,"title":["High-Performance Parallel Implementation of Genetic Algorithm on FPGA"],"prefix":"10.1007","volume":"38","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6356-3538","authenticated-orcid":false,"given":"Matheus F.","family":"Torquato","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7536-2506","authenticated-orcid":false,"given":"Marcelo A. C.","family":"Fernandes","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2019,1,21]]},"reference":[{"issue":"7","key":"1037_CR1","doi-asserted-by":"publisher","first-page":"1551","DOI":"10.1109\/TCYB.2015.2451595","volume":"46","author":"SPH Alinodehi","year":"2016","unstructured":"S.P.H. Alinodehi, S. Moshfe, M.S. Zaeimian, A. Khoei, K. Hadidi, High-speed general purpose genetic algorithm processor. IEEE Trans. Cybern. 46(7), 1551\u20131565 (2016)","journal-title":"IEEE Trans. Cybern."},{"key":"1037_CR2","doi-asserted-by":"publisher","first-page":"378","DOI":"10.1016\/j.asoc.2017.04.015","volume":"58","author":"MSB Ameur","year":"2017","unstructured":"M.S.B. Ameur, A. Sakly, Fpga based hardware implementation of bat algorithm. Appl. Soft Comput. 58, 378\u2013387 (2017)","journal-title":"Appl. Soft Comput."},{"key":"1037_CR3","unstructured":"K. Chapman, Multiplexer design techniques for datapath performance with minimized routing resources, in Application Note: Spartan-6 Family, Virtex-6 Family, 7 Series FPGAs (2014)"},{"key":"1037_CR4","unstructured":"Y. Chen, Q. Wu, Design and implementation of PID controller based on FPGA and genetic algorithm, in 2011 International Conference on Electronics and Optoelectronics (ICEOE), vol.\u00a04, p. V4\u2013308. IEEE (2011)"},{"issue":"11","key":"1037_CR5","doi-asserted-by":"publisher","first-page":"1149","DOI":"10.1080\/00207210802387494","volume":"95","author":"K Deliparaschos","year":"2008","unstructured":"K. Deliparaschos, G. Doyamis, S. Tzafestas, A parameterised genetic algorithm IP core: FPGA design, implementation and performance evaluation. Int. J. Electron. 95(11), 1149\u20131166 (2008)","journal-title":"Int. J. Electron."},{"key":"1037_CR6","unstructured":"P. Fernando, H. Sankaran, S. Katkoori, D. Keymeulen, A. Stoica, R. Zebulum, R. Rajeshuni, A customizable FPGA IP core implementation of a general purpose genetic algorithm engine, in IEEE International Symposium on Parallel and Distributed Processing, 2008. IPDPS 2008 (IEEE, 2008), p. 1\u20138"},{"issue":"1","key":"1037_CR7","doi-asserted-by":"publisher","first-page":"133","DOI":"10.1109\/TEVC.2009.2025032","volume":"14","author":"PR Fernando","year":"2010","unstructured":"P.R. Fernando, S. Katkoori, D. Keymeulen, R. Zebulum, A. Stoica, Customizable FPGA IP core implementation of a general-purpose genetic algorithm engine. IEEE Trans. Evolut. Comput. 14(1), 133\u2013149 (2010). \n                    https:\/\/doi.org\/10.1109\/TEVC.2009.2025032","journal-title":"IEEE Trans. Evolut. Comput."},{"issue":"4","key":"1037_CR8","doi-asserted-by":"publisher","first-page":"1649","DOI":"10.1109\/TIT.2006.871045","volume":"52","author":"M Goresky","year":"2006","unstructured":"M. Goresky, A. Klapper, Pseudonoise sequences based on algebraic feedback shift registers. IEEE Trans. Inf. Theory 52(4), 1649\u20131662 (2006)","journal-title":"IEEE Trans. Inf. Theory"},{"issue":"4","key":"1037_CR9","doi-asserted-by":"publisher","first-page":"86","DOI":"10.1145\/2927964.2927980","volume":"43","author":"L Guo","year":"2016","unstructured":"L. Guo, A.I. Funie, D.B. Thomas, H. Fu, W. Luk, Parallel genetic algorithms on multiple fpgas. ACM SIGARCH Comput. Arch. News 43(4), 86\u201393 (2016)","journal-title":"ACM SIGARCH Comput. Arch. News"},{"issue":"6","key":"1037_CR10","doi-asserted-by":"publisher","first-page":"361","DOI":"10.1504\/IJBIC.2015.073183","volume":"7","author":"L Guo","year":"2015","unstructured":"L. Guo, A.I. Funie, Z. Xie, D. Thomas, W. Luk, A general-purpose framework for FPGA-accelerated genetic algorithms. Int. J. Bio-Inspir. Comput. 7(6), 361\u2013375 (2015)","journal-title":"Int. J. Bio-Inspir. Comput."},{"key":"1037_CR11","volume-title":"Adaptation in Natural and Artificial Systems: An Introductory Analysis with Applications to Biology, Control, and Artificial Intelligence","author":"JH Holland","year":"1975","unstructured":"J.H. Holland, Adaptation in Natural and Artificial Systems: An Introductory Analysis with Applications to Biology, Control, and Artificial Intelligence (U Michigan Press, Ann Arbor, 1975)"},{"key":"1037_CR12","unstructured":"N. Instruments, Understanding parallel hardware: multiprocessors, hyperthreading, dual-core, multicore and FPGAs (2011). \n                    http:\/\/www.ni.com\/tutorial\/6097\/en\/"},{"key":"1037_CR13","doi-asserted-by":"crossref","unstructured":"L.M. Ionescu, A. Mazare, A.I. Lita, G. Serban, Fully integrated artificial intelligence solution for real time route tracking, in 2015 38th International Spring Seminar on Electronics Technology (ISSE) (IEEE, 2015), p. 536\u2013540","DOI":"10.1109\/ISSE.2015.7248059"},{"key":"1037_CR14","doi-asserted-by":"crossref","unstructured":"Y. Jewajinda, P. Chongstitvatana, Hardware architecture and FPGA implementation of a parallel elitism-based compact genetic algorithm, in TENCON 2009-2009 IEEE Region 10 Conference (IEEE, 2009), p. 1\u20136","DOI":"10.1109\/TENCON.2009.5396138"},{"issue":"10","key":"1037_CR15","first-page":"603","volume":"II","author":"JR Koza","year":"1991","unstructured":"J.R. Koza, Genetic evolution and co-evolution of computer programs. Artif. Life II(10), 603\u2013629 (1991)","journal-title":"Artif. Life"},{"key":"1037_CR16","unstructured":"A. Lotfi, A. Rahimi, A. Yazdanbakhsh, H. Esmaeilzadeh, R.K. Gupta, Grater: an approximation workflow for exploiting data-level parallelism in FPGA acceleration. In: 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) (IEEE, 2016), p. 1279\u20131284"},{"key":"1037_CR17","doi-asserted-by":"crossref","unstructured":"F. Mengxu, T. Bin, FPGA implementation of an adaptive genetic algorithm, in 2015 12th International Conference on Service Systems and Service Management (ICSSSM) (IEEE, 2015), p. 1\u20135","DOI":"10.1109\/ICSSSM.2015.7170318"},{"key":"1037_CR18","doi-asserted-by":"crossref","unstructured":"H. Merabti, D. Massicotte, Hardware implementation of a real-time genetic algorithm for adaptive filtering applications, in 2014 IEEE 27th Canadian Conference on Electrical and Computer Engineering (CCECE) (IEEE, 2014), p. 1\u20135","DOI":"10.1109\/CCECE.2014.6900991"},{"issue":"3","key":"1037_CR19","doi-asserted-by":"publisher","first-page":"190","DOI":"10.1016\/j.micpro.2011.12.002","volume":"36","author":"G Mingas","year":"2012","unstructured":"G. Mingas, E. Tsardoulias, L. Petrou, An fpga implementation of the SMG-SLAM algorithm. Microprocess. Microsyst. 36(3), 190\u2013204 (2012)","journal-title":"Microprocess. Microsyst."},{"issue":"9","key":"1037_CR20","doi-asserted-by":"publisher","first-page":"863","DOI":"10.1007\/s00607-013-0305-5","volume":"95","author":"VP Nambiar","year":"2013","unstructured":"V.P. Nambiar, S. Balakrishnan, M. Khalil-Hani, M.N. Marsono, Hw\/sw co-design of reconfigurable hardware-based genetic algorithm in FPGAs applicable to a variety of problems. Computing 95(9), 863\u2013896 (2013)","journal-title":"Computing"},{"issue":"1","key":"1037_CR21","doi-asserted-by":"publisher","first-page":"88","DOI":"10.1016\/j.neucom.2006.11.032","volume":"71","author":"N Nedjah","year":"2007","unstructured":"N. Nedjah, L. de Macedo Mourelle, An efficient problem-independent hardware implementation of genetic algorithms. Neurocomputing 71(1), 88\u201394 (2007)","journal-title":"Neurocomputing"},{"key":"1037_CR22","doi-asserted-by":"crossref","unstructured":"T.C. Oliveira, V.P. J\u00fanior, An implementation of compact genetic algorithm on FPGA for extrinsic evolvable hardware, in 2008 4th Southern Conference on Programmable Logic (IEEE, 2008), p. 187\u2013190","DOI":"10.1109\/SPL.2008.4547754"},{"key":"1037_CR23","doi-asserted-by":"publisher","first-page":"1066","DOI":"10.1016\/j.asoc.2017.09.044","volume":"62","author":"M Peker","year":"2018","unstructured":"M. Peker, A fully customizable hardware implementation for general purpose genetic algorithms. Appl. Soft Comput. 62, 1066\u20131076 (2018)","journal-title":"Appl. Soft Comput."},{"key":"1037_CR24","doi-asserted-by":"publisher","first-page":"509","DOI":"10.1016\/j.neucom.2013.04.020","volume":"120","author":"H Qu","year":"2013","unstructured":"H. Qu, K. Xing, T. Alexander, An improved genetic algorithm with co-evolutionary strategy for global path planning of multiple mobile robots. Neurocomputing 120, 509\u2013517 (2013)","journal-title":"Neurocomputing"},{"key":"1037_CR25","unstructured":"N.M. Razali, J. Geraghty, Genetic algorithm performance with different selection strategies in solving TSP, in Proceedings of the World Congress on Engineering, vol. 2 (International Association of Engineers, Hong Kong, 2011), pp. 1134\u20131139"},{"issue":"11","key":"1037_CR26","doi-asserted-by":"publisher","first-page":"3140","DOI":"10.1109\/TC.2015.2401015","volume":"64","author":"A Rodriguez","year":"2015","unstructured":"A. Rodriguez, F. Moreno, Evolutionary computing and particle filtering: a hardware-based motion estimation system. IEEE Trans. Comput. 64(11), 3140\u20133152 (2015)","journal-title":"IEEE Trans. Comput."},{"key":"1037_CR27","doi-asserted-by":"publisher","unstructured":"S.D. Scott, A. Samal, S. Seth, Hga: a hardware-based genetic algorithm, in 3rd International ACM Symposium on Field-Programmable Gate Arrays (1995), p. 53\u201359. \n                    https:\/\/doi.org\/10.1109\/FPGA.1995.241945","DOI":"10.1109\/FPGA.1995.241945"},{"key":"1037_CR28","doi-asserted-by":"crossref","unstructured":"N. Sehatbakhsh, M. Aliasgari, S.M. Fakhraie, Fpga implementation of genetic algorithm for dynamic filter-bank-based multicarrier systems, in 2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) (IEEE, 2013), p. 72\u201377","DOI":"10.1109\/DTIS.2013.6527781"},{"issue":"4","key":"1037_CR29","doi-asserted-by":"publisher","first-page":"443","DOI":"10.1002\/cpe.1113","volume":"19","author":"V Tirumalai","year":"2007","unstructured":"V. Tirumalai, K.G. Ricks, K.A. Woodbury, Using parallelization and hardware concurrency to improve the performance of a genetic algorithm. Concurr. Comput. Pract. Exp. 19(4), 443\u2013462 (2007)","journal-title":"Concurr. Comput. Pract. Exp."},{"key":"1037_CR30","volume-title":"Introduction to VLSI Circuits and Systems","author":"JP Uyemura","year":"2002","unstructured":"J.P. Uyemura, Introduction to VLSI Circuits and Systems (Wiley, Hoboken, 2002)"},{"key":"1037_CR31","doi-asserted-by":"crossref","unstructured":"M. Vavouras, K. Papadimitriou, I. Papaefstathiou, High-speed FPGA-based implementations of a genetic algorithm, in: International Symposium on Systems, Architectures, Modeling, and Simulation, 2009. SAMOS\u201909, p. 9\u201316. (IEEE, 2009)","DOI":"10.1109\/ICSAMOS.2009.5289236"},{"key":"1037_CR32","doi-asserted-by":"crossref","unstructured":"Z. Yan-cong, G. Jun-hua, D. Yong-feng, H. Huan-ping, Implementation of genetic algorithm for tsp based on FPGA, in: 2011 Chinese Control and Decision Conference (CCDC) (IEEE, 2011), p. 2226\u20132231","DOI":"10.1109\/CCDC.2011.5968577"},{"issue":"1","key":"1037_CR33","doi-asserted-by":"publisher","first-page":"95","DOI":"10.1016\/j.neucom.2006.11.031","volume":"71","author":"Z Zhu","year":"2007","unstructured":"Z. Zhu, D.J. Mulvaney, V.A. Chouliaras, Hardware implementation of a novel genetic algorithm. Neurocomputing 71(1), 95\u2013106 (2007)","journal-title":"Neurocomputing"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s00034-019-01037-w\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-019-01037-w.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-019-01037-w.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,1,20]],"date-time":"2020-01-20T19:17:52Z","timestamp":1579547872000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s00034-019-01037-w"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,1,21]]},"references-count":33,"journal-issue":{"issue":"9","published-print":{"date-parts":[[2019,9]]}},"alternative-id":["1037"],"URL":"https:\/\/doi.org\/10.1007\/s00034-019-01037-w","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"value":"0278-081X","type":"print"},{"value":"1531-5878","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,1,21]]},"assertion":[{"value":"4 July 2018","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"11 January 2019","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"14 January 2019","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"21 January 2019","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}