{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,6]],"date-time":"2025-12-06T17:08:27Z","timestamp":1765040907693,"version":"3.37.3"},"reference-count":43,"publisher":"Springer Science and Business Media LLC","issue":"9","license":[{"start":{"date-parts":[[2019,2,22]],"date-time":"2019-02-22T00:00:00Z","timestamp":1550793600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2019,9]]},"DOI":"10.1007\/s00034-019-01063-8","type":"journal-article","created":{"date-parts":[[2019,2,22]],"date-time":"2019-02-22T11:07:30Z","timestamp":1550833650000},"page":"4280-4301","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":28,"title":["Analytical Review of Noise Margin in MVL: Clarification of a Deceptive Matter"],"prefix":"10.1007","volume":"38","author":[{"given":"Mehdi","family":"Takbiri","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7175-0229","authenticated-orcid":false,"given":"Reza","family":"Faghih Mirzaee","sequence":"additional","affiliation":[]},{"given":"Keivan","family":"Navi","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2019,2,22]]},"reference":[{"key":"1063_CR1","doi-asserted-by":"publisher","first-page":"44","DOI":"10.1016\/j.mejo.2016.10.009","volume":"58","author":"E Abiri","year":"2016","unstructured":"E. Abiri, A. Darabi, A novel design of low power and high read stability ternary SRAM (T-SRAM), memory based on the modified gate diffusion input (m-GDI) method in nanotechnology. Microelectron. J. 58, 44\u201359 (2016)","journal-title":"Microelectron. J."},{"key":"1063_CR2","doi-asserted-by":"publisher","first-page":"142","DOI":"10.1016\/j.compeleceng.2018.05.019","volume":"69","author":"E Abiri","year":"2018","unstructured":"E. Abiri, A. Darabi, S. Salem, Design of multiple-valued logic gates using gate-diffusion input for image processing applications. Comput. Electr. Eng. 69, 142\u2013157 (2018)","journal-title":"Comput. Electr. Eng."},{"key":"1063_CR3","doi-asserted-by":"crossref","first-page":"37","DOI":"10.1007\/1-4020-2888-1","volume-title":"Current-Mode Digital Circuits: Model and Design of Bipolar and MOS Current-Mode Logic","author":"M Alioto","year":"2005","unstructured":"M. Alioto, G. Palumbo, Current-Mode Digital Circuits: Model and Design of Bipolar and MOS Current-Mode Logic (Springer, Dordrecht, 2005), pp. 37\u201346"},{"key":"1063_CR4","doi-asserted-by":"publisher","first-page":"358","DOI":"10.1016\/j.microrel.2014.11.011","volume":"55","author":"CG Almudever","year":"2015","unstructured":"C.G. Almudever, A. Rubio, Variability and reliability analysis of CNFET technology: impact of manufacturing imperfections. Microelectron. Reliab. 55, 358\u2013366 (2015)","journal-title":"Microelectron. Reliab."},{"key":"1063_CR5","doi-asserted-by":"publisher","first-page":"2613","DOI":"10.1016\/j.microrel.2014.05.009","volume":"54","author":"B Alorda","year":"2014","unstructured":"B. Alorda, G. Torrens, S. Bota, J. Segura, Adaptive static and dynamic noise margin improvement in minimum-sized 6T-SRAM cells. Microelectron. Reliab. 54, 2613\u20132620 (2014)","journal-title":"Microelectron. Reliab."},{"key":"1063_CR6","unstructured":"V. Beiu, M. Tache, Statistical analysis of static noise margins, in European Conference on Circuit Theory and Design (2015), pp. 1\u20134"},{"key":"1063_CR7","doi-asserted-by":"publisher","first-page":"97","DOI":"10.1016\/j.vlsi.2016.02.003","volume":"54","author":"G Cho","year":"2016","unstructured":"G. Cho, F. Lombardi, Design and process variation analysis of CNTFET-based ternary memory cells. Integr. VLSI J. 54, 97\u2013108 (2016)","journal-title":"Integr. VLSI J."},{"key":"1063_CR8","unstructured":"J. Deng, Device modeling and circuit performance evaluation for nanoscale devices: silicon technology beyond 45\u00a0nm node and carbon nanotube field effect transistors. Ph.D. Thesis, Stanford University (2007)"},{"key":"1063_CR9","unstructured":"E. Dubrova, Multiple-valued logic in VLSI: challenges and opportunities, in Proceeding of the NORCHIP\u201999 (1999), pp. 340\u2013350"},{"key":"1063_CR10","doi-asserted-by":"publisher","first-page":"156","DOI":"10.1016\/j.mejo.2016.04.016","volume":"53","author":"SA Ebrahimi","year":"2016","unstructured":"S.A. Ebrahimi, M.R. Reshadinezhad, A. Bohlooli, M. Shahsavari, Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits. Microelectron. J. 53, 156\u2013166 (2016)","journal-title":"Microelectron. J."},{"key":"1063_CR11","doi-asserted-by":"publisher","first-page":"1238","DOI":"10.1016\/j.mejo.2013.08.010","volume":"44","author":"R Faghih Mirzaee","year":"2013","unstructured":"R. Faghih Mirzaee, T. Nikoubin, K. Navi, O. Hashemipour, Differential cascode voltage switch (DCVS) strategies by CNTFET technology for standard ternary logic. Microelectron. J. 44, 1238\u20131250 (2013)","journal-title":"Microelectron. J."},{"key":"1063_CR12","unstructured":"S. Farhana, M.F. Noordin, Technology and performance: carbon nanotube (CNT) field effect transistor (FET) in VLSI circuit design, in IEEE 7th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (2016), pp. 1\u20134"},{"key":"1063_CR13","unstructured":"P.A. Gowrisankar, Design of multi-valued ternary logic gates based on emerging sub-32\u00a0nm technology, in 3rd International Conference on Science Technology Engineering & Management (2017), pp. 1023\u20131031"},{"key":"1063_CR14","doi-asserted-by":"publisher","first-page":"363","DOI":"10.1109\/13.241612","volume":"36","author":"JR Hauser","year":"1993","unstructured":"J.R. Hauser, Noise margin criteria for digital logic circuits. IEEE Trans. Educ. 36, 363\u2013368 (1993)","journal-title":"IEEE Trans. Educ."},{"key":"1063_CR15","unstructured":"H. Inokawa, A. Fujiwara, Y. Takahashi, A multiple-valued logic with merged single-electron and MOS transistors, in Proceedings of the International Electron Devices Meeting (2001), pp. 7.2.1\u20137.2.4"},{"key":"1063_CR16","unstructured":"International Symposium on Multiple-Valued Logic. \n                    https:\/\/ieeexplore.ieee.org\/xpl\/conhome.jsp?punumber=1000485"},{"key":"1063_CR17","unstructured":"ITRS, Albany, NY, USA, 2013, \n                    http:\/\/www.itrs2.net"},{"key":"1063_CR18","doi-asserted-by":"publisher","first-page":"793","DOI":"10.1109\/TVLSI.2012.2198248","volume":"21","author":"S Karmakar","year":"2013","unstructured":"S. Karmakar, A. Chandy, F.C. Jain, Design of ternary logic combinational circuits based on quantum dot gate FETs. IEEE Trans. Very Large Scale Integr. Syst. 21, 793\u2013806 (2013)","journal-title":"Very Large Scale Integr. Syst."},{"key":"1063_CR19","first-page":"93","volume":"12","author":"K Kuhn","year":"2008","unstructured":"K. Kuhn, C. Kenyon, A. Kornfeld, M. Liu, A. Maheshwari, W. Shih, S. Sivakumar, G. Taylor, P. Vandervoorn, K. Zawadzki, Managing process variation in Intel\u2019s 45\u00a0nm CMOS technology. Intel Technol. J. 12, 93\u2013109 (2008)","journal-title":"Intel Technol. J."},{"key":"1063_CR20","doi-asserted-by":"publisher","first-page":"547","DOI":"10.1016\/j.microrel.2009.12.003","volume":"50","author":"KF Lee","year":"2010","unstructured":"K.F. Lee, Y. Li, T.Y. Li, Z.C. Su, C.H. Hwang, Device and circuit level suppression techniques for random-dopant-induced static noise margin fluctuation in 16-nm-gate SRAM cell. Microelectron. Reliab. 50, 547\u2013651 (2010)","journal-title":"Microelectron. Reliab."},{"key":"1063_CR21","first-page":"1","volume":"39","author":"G Li","year":"2018","unstructured":"G. Li, P. Wang, Y. Kang, Y. Zhang, A low standby-power fast carbon nanotube ternary SRAM cell with improved stability. J. Semicond. 39, 1\u20137 (2018)","journal-title":"J. Semicond."},{"key":"1063_CR22","doi-asserted-by":"publisher","first-page":"695","DOI":"10.1109\/TNANO.2014.2316000","volume":"13","author":"J Liang","year":"2014","unstructured":"J. Liang, L. Chen, J. Han, F. Lombardi, Design and evaluation of multiple valued logic gates using pseudo N-type carbon nanotube FETs. IEEE Trans. Nanotechnol. 13, 695\u2013708 (2014)","journal-title":"IEEE Trans. Nanotechnol."},{"key":"1063_CR23","doi-asserted-by":"publisher","first-page":"217","DOI":"10.1109\/TNANO.2009.2036845","volume":"10","author":"S Lin","year":"2011","unstructured":"S. Lin, Y. Kim, F. Lombardi, CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans. Nanotechnol. 10, 217\u2013225 (2011)","journal-title":"IEEE Trans. Nanotechnol."},{"key":"1063_CR24","doi-asserted-by":"publisher","first-page":"1019","DOI":"10.1109\/TNANO.2011.2179062","volume":"11","author":"S Lin","year":"2012","unstructured":"S. Lin, Y.-B. Kim, F. Lombardi, Design of a ternary memory cell using CNTFETs. IEEE Trans. Nanotechnol. 11, 1019\u20131025 (2012)","journal-title":"IEEE Trans. Nanotechnol."},{"key":"1063_CR25","doi-asserted-by":"publisher","first-page":"110","DOI":"10.1166\/jctn.2014.3324","volume":"11","author":"M Maleknejad","year":"2014","unstructured":"M. Maleknejad, R. Faghih Mirzaee, K. Navi, O. Hashemipour, Multi-Vt ternary circuits by carbon nanotube field effect transistor technology for low-voltage and low-power applications. J. Comput. Theor. Nanosci. 11, 110\u2013118 (2014)","journal-title":"J. Comput. Theor. Nanosci."},{"key":"1063_CR26","unstructured":"R. Mariani, F. Pessolano, R. Saletti, A new CMOS ternary logic design for low-power low-voltage circuits, in Proceedings of the 7th International Workshop on Power, Timing, Modeling, Optimization, and Simulation (1997), pp. 173\u2013185"},{"key":"1063_CR27","first-page":"854","volume":"8","author":"R Marani","year":"2015","unstructured":"R. Marani, A.G. Perri, The next generation of FETs: CNTFETs. Int. J. Adv. Eng. Technol. 8, 854\u2013866 (2015)","journal-title":"Int. J. Adv. Eng. Technol."},{"key":"1063_CR28","doi-asserted-by":"publisher","first-page":"285","DOI":"10.1049\/iet-cds.2010.0340","volume":"5","author":"MH Moaiyeri","year":"2011","unstructured":"M.H. Moaiyeri, A. Doostaregan, K. Navi, Design of energy-efficient and robust ternary circuits for nanotechnology. IET Circuits Devices Syst. 5, 285\u2013296 (2011)","journal-title":"IET Circuits Devices Syst."},{"key":"1063_CR29","doi-asserted-by":"publisher","first-page":"1631","DOI":"10.1007\/s00034-012-9413-2","volume":"31","author":"MH Moaiyeri","year":"2012","unstructured":"M.H. Moaiyeri, K. Navi, O. Hashemipour, Design and evaluation of CNFET-based quaternary circuits. Circuits Syst Signal Process. 31, 1631\u20131652 (2012)","journal-title":"Circuits Syst Signal Process."},{"key":"1063_CR30","doi-asserted-by":"publisher","first-page":"617","DOI":"10.1166\/jno.2018.2145","volume":"13","author":"MH Moaiyeri","year":"2018","unstructured":"M.H. Moaiyeri, H. Akbari, M. Moghaddam, An ultra-low-power and robust ternary static random access memory cell based on carbon nanotube FETs. J. Nanoelectron. Optoelectron. 13, 617\u2013627 (2018)","journal-title":"J. Nanoelectron. Optoelectron."},{"key":"1063_CR31","unstructured":"H. Nan, K. Choi, Novel ternary logic design based on CNFET, in International SoC Design Conferenece (2010), pp. 115\u2013118"},{"key":"1063_CR32","doi-asserted-by":"publisher","first-page":"172","DOI":"10.1109\/TDMR.2017.2667619","volume":"17","author":"M Rana","year":"2017","unstructured":"M. Rana, R. Canal, E. Amat, A. Rubio, Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation. IEEE Trans. Device Mater. Reliab. 17, 172\u2013182 (2017)","journal-title":"IEEE Trans. Device Mater. Reliab."},{"key":"1063_CR33","doi-asserted-by":"publisher","first-page":"168","DOI":"10.1109\/TNANO.2004.842068","volume":"4","author":"A Raychowdhury","year":"2005","unstructured":"A. Raychowdhury, K. Roy, Carbon-nanotube-based voltage-mode multiple-valued logic design. IEEE Trans. Nanotechnol. 4, 168\u2013179 (2005)","journal-title":"IEEE Trans. Nanotechnol."},{"key":"1063_CR34","doi-asserted-by":"publisher","first-page":"41","DOI":"10.1016\/j.mejo.2017.02.018","volume":"63","author":"H Samadi","year":"2017","unstructured":"H. Samadi, A. Shahhoseini, F. Aghaei-liavali, A new method on designing and simulating CNTFET_based ternary gates and arithmetic circuits. Microelectron. J. 63, 41\u201348 (2017)","journal-title":"Microelectron. J."},{"key":"1063_CR35","unstructured":"H. Shahidipour, A. Ahmadi, K. Maharatna, Effect of variability in SWCNT-based logic gates, in Proceedings of the International Symposium Integrated Circuits (2009), pp. 252\u2013255"},{"key":"1063_CR36","doi-asserted-by":"publisher","first-page":"762","DOI":"10.1007\/s10825-015-0714-0","volume":"14","author":"F Sharifi","year":"2015","unstructured":"F. Sharifi, M.H. Moaiyeri, K. Navi, N. Bagherzadeh, Quaternary full adder cells based on carbon nanotube FETs. J. Comput. Electron. 14, 762\u2013772 (2015)","journal-title":"J. Comput. Electron."},{"key":"1063_CR37","doi-asserted-by":"publisher","first-page":"1333","DOI":"10.1016\/j.mejo.2015.09.018","volume":"46","author":"F Sharifi","year":"2015","unstructured":"F. Sharifi, M.H. Moaiyeri, K. Navi, N. Bagherzadeh, Robust and energy-efficient carbon nanotube FET-based MVL gates. Microelectron. J. 46, 1333\u20131342 (2015)","journal-title":"Microelectron. J."},{"key":"1063_CR38","unstructured":"S. Shin, E. Jang, J.W. Jeong, K.R. Kim, CMOS-compatible ternary device platform for physical synthesis of multi-valued logic circuits, in 47th International Symposium Multiple-Valued Logic (2017), pp. 284\u2013289"},{"key":"1063_CR39","unstructured":"S. Shreya, S. Sourav, Design, analysis and comparison between CNTFET based ternary SRAM cell and PCRAM cell, in International Conference on Communication, Control and Intelligent Systems (2015), pp. 347\u2013351"},{"key":"1063_CR40","first-page":"13","volume":"58","author":"E Sipos","year":"2017","unstructured":"E. Sipos, R. Groza, L.N. Ivanciu, Power consumption and noise margin comparison between simple ternary inverter and binary inverter. Acta Tech. Napoc. Electron. Telecommun. 58, 13\u201316 (2017)","journal-title":"Acta Tech. Napoc. Electron. Telecommun."},{"key":"1063_CR41","unstructured":"Stanford CNFET Model, \n                    https:\/\/nano.stanford.edu\/stanford-cnfet-model"},{"key":"1063_CR42","unstructured":"S. Tabrizchi, F. Sharifi, A.-H. Badawy, Z.M. Saifullah, Enabling energy-efficient ternary logic gates using CNFETs, in IEEE 17th International Conference on Nanotechnology (2017), pp. 542\u2013547"},{"key":"1063_CR43","doi-asserted-by":"publisher","first-page":"381","DOI":"10.1049\/mnl.2011.0168","volume":"6","author":"K You","year":"2011","unstructured":"K. You, K. Nepal, Design of a ternary static memory cell using carbon nanotube-based transistors. IET Micro Nano Lett. 6, 381\u2013385 (2011)","journal-title":"IET Micro Nano Lett."}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s00034-019-01063-8\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-019-01063-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-019-01063-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,2,21]],"date-time":"2020-02-21T19:05:59Z","timestamp":1582311959000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s00034-019-01063-8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,2,22]]},"references-count":43,"journal-issue":{"issue":"9","published-print":{"date-parts":[[2019,9]]}},"alternative-id":["1063"],"URL":"https:\/\/doi.org\/10.1007\/s00034-019-01063-8","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"type":"print","value":"0278-081X"},{"type":"electronic","value":"1531-5878"}],"subject":[],"published":{"date-parts":[[2019,2,22]]},"assertion":[{"value":"11 February 2018","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"9 February 2019","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"12 February 2019","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"22 February 2019","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}