{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,4,26]],"date-time":"2024-04-26T21:13:32Z","timestamp":1714166012064},"reference-count":17,"publisher":"Springer Science and Business Media LLC","issue":"12","license":[{"start":{"date-parts":[[2019,6,11]],"date-time":"2019-06-11T00:00:00Z","timestamp":1560211200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2019,6,11]],"date-time":"2019-06-11T00:00:00Z","timestamp":1560211200000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"funder":[{"name":"the National Natural Science Foundation of China under Grant","award":["NO:41275027&NO:11504121"],"award-info":[{"award-number":["NO:41275027&NO:11504121"]}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2019,12]]},"DOI":"10.1007\/s00034-019-01163-5","type":"journal-article","created":{"date-parts":[[2019,6,11]],"date-time":"2019-06-11T15:10:33Z","timestamp":1560265833000},"page":"5817-5838","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Theory of Expansion Boolean Algebra and Its Applications in CMOS VLSI Digital Systems"],"prefix":"10.1007","volume":"38","author":[{"given":"En-hua","family":"Jiang","sequence":"first","affiliation":[]},{"given":"Wen-bin","family":"Jiang","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2019,6,11]]},"reference":[{"issue":"10","key":"1163_CR1","doi-asserted-by":"publisher","first-page":"2001","DOI":"10.1109\/TVLSI.2014.2357057","volume":"23","author":"P Bhattacharyya","year":"2015","unstructured":"P. Bhattacharyya, B. Kundu, S. Ghosh, V. Kumar, A. Dandapat, Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23(10), 2001\u20132008 (2015)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"12","key":"1163_CR2","doi-asserted-by":"publisher","first-page":"1309","DOI":"10.1109\/TVLSI.2006.887807","volume":"14","author":"S Goel","year":"2006","unstructured":"S. Goel, A. Kumar, M.A. Bayoumi, Design of robust, energy-efficient full adders for deep-submicrometer design suing hybrid-CMOS logic style. IEEE Trans. VLSI Syst. 14(12), 1309\u20131321 (2006)","journal-title":"IEEE Trans. VLSI Syst."},{"issue":"7","key":"1163_CR3","doi-asserted-by":"publisher","first-page":"602","DOI":"10.1109\/TC.1986.1676801","volume":"C-35","author":"JP Hayes","year":"1986","unstructured":"J.P. Hayes, Pseudo-Boolean logic circuits. IEEE Trans. Comput. C-35(7), 602\u2013612 (1986)","journal-title":"IEEE Trans. Comput."},{"issue":"7","key":"1163_CR4","doi-asserted-by":"publisher","first-page":"345","DOI":"10.1109\/TCSII.2004.831429","volume":"51","author":"Y Jiang","year":"2004","unstructured":"Y. Jiang, A. Al-Sheraidah, Y. Wing et al., A novel multiplexer-based low power full adder. IEEE Trans. Circuits Syst. II Express Briefs 51(7), 345\u2013348 (2004)","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"key":"1163_CR5","volume-title":"Leblebigi, CMOS Digital Integrated Circuit: Analysis and Design","author":"S Kang","year":"2003","unstructured":"S. Kang, Y. Leblebigi, CMOS Digital Integrated Circuit: Analysis and Design, 3rd edn. (McGraw-Hill, New York, 2003)","edition":"3"},{"issue":"3","key":"1163_CR6","first-page":"509","volume":"29","author":"H Lee","year":"1998","unstructured":"H. Lee, G.E. Sobelman, New XOR\/XNOR and full adder circuits for low-voltage low-power applications. Microelectron. J. 29(3), 509\u2013517 (1998)","journal-title":"Microelectron. J."},{"issue":"8","key":"1163_CR7","doi-asserted-by":"publisher","first-page":"1481","DOI":"10.1109\/TVLSI.2018.2820999","volume":"26","author":"H Naseri","year":"2018","unstructured":"H. Naseri, S. Timarchi, Low-power and fast full adder by exploring new XOR and XNOR. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 26(8), 1481\u20131493 (2018)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"4","key":"1163_CR8","doi-asserted-by":"publisher","first-page":"457","DOI":"10.1016\/j.vlsi.2009.02.001","volume":"42","author":"K Navi","year":"2009","unstructured":"K. Navi, M. Maeen, V. Foroutan et al., A novel low power full-adder cell for low voltage. Integr. VLSI J. 42(4), 457\u2013467 (2009)","journal-title":"Integr. VLSI J."},{"key":"1163_CR9","doi-asserted-by":"publisher","first-page":"551","DOI":"10.1109\/ASPDAC.1997.600333","volume":"1","author":"M Pedran","year":"1997","unstructured":"M. Pedran, X. Wu, A new description of CMOS circuits at switch-level. Proc. IEEE 1, 551\u2013556 (1997). \n                    https:\/\/doi.org\/10.1109\/ASPDAC.1997.600333","journal-title":"Proc. IEEE"},{"issue":"7","key":"1163_CR10","doi-asserted-by":"publisher","first-page":"775","DOI":"10.1109\/43.3948","volume":"7","author":"C Pedron","year":"1988","unstructured":"C. Pedron, A. Stauffer, Analysis and synthesis of combinational pass transistor circuits. IEEE Trans. Comput. Aided Des. 7(7), 775\u2013786 (1988)","journal-title":"IEEE Trans. Comput. Aided Des."},{"issue":"1","key":"1163_CR11","doi-asserted-by":"publisher","first-page":"19","DOI":"10.1049\/ip-cds:20010170","volume":"148","author":"D Radhakrishnun","year":"2001","unstructured":"D. Radhakrishnun, Low voltage low power CMOS full adder. IEE Proc. Circuits Dev. Syst. 148(1), 19\u201324 (2001)","journal-title":"IEE Proc. Circuits Dev. Syst."},{"issue":"5","key":"1163_CR12","doi-asserted-by":"publisher","first-page":"478","DOI":"10.1109\/82.842117","volume":"47","author":"AM Shams","year":"2000","unstructured":"A.M. Shams, M.A. Bayoumi, A novel high performance CMOS 1-bit full adder cell. IEEE Trans. Circuits Syst. II Analog Digit. Signal Process. 47(5), 478\u2013481 (2000)","journal-title":"IEEE Trans. Circuits Syst. II Analog Digit. Signal Process."},{"issue":"1","key":"1163_CR13","doi-asserted-by":"publisher","first-page":"20","DOI":"10.1109\/92.988727","volume":"10","author":"AM Shams","year":"2002","unstructured":"A.M. Shams, T.K. Darwish, M.A. Bayoumi, Performance analysis of low-power 1 bit CMOS full-adder cells. IEEE Trans. Very Large Scale Integr. Syst. 10(1), 20\u201329 (2002)","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"1163_CR14","unstructured":"M.A. Valashani, S. Mirzakuchaki, A novel fast, low-power and high-performance XOR-XNOR cell, in Proceedings of the IEEE International Symposium Circuits System (ISCAS), Vol. 1 (2016), pp. 694\u2013697"},{"key":"1163_CR15","unstructured":"M. Vesterbacka, A 14-transistor CMOS full adder with full voltage-swing nodes, in Proceedings of the IEEE Workshop Signal Processing System (Sips) (1999), pp. 713\u2013722"},{"issue":"2","key":"1163_CR16","first-page":"78","volume":"2","author":"S Wairya","year":"2011","unstructured":"S. Wairya, R.K. Nagaria, S. Tiwari, New design methodologies for high-speed mixed-mode CMOS full adder circuits. Int. J. VLSI Des. Commun. Syst. (VLSICS) 2(2), 78\u201398 (2011)","journal-title":"Int. J. VLSI Des. Commun. Syst. (VLSICS)"},{"issue":"7","key":"1163_CR17","doi-asserted-by":"publisher","first-page":"1079","DOI":"10.1109\/4.597298","volume":"32","author":"R Zimmermann","year":"1997","unstructured":"R. Zimmermann, W. Fichtner, low-power styles: CMOS versus pass-transistor logic. IEEE J. Solid State Circuits 32(7), 1079\u20131090 (1997)","journal-title":"IEEE J. Solid State Circuits"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-019-01163-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s00034-019-01163-5\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-019-01163-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,6,9]],"date-time":"2020-06-09T23:12:46Z","timestamp":1591744366000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s00034-019-01163-5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,6,11]]},"references-count":17,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2019,12]]}},"alternative-id":["1163"],"URL":"https:\/\/doi.org\/10.1007\/s00034-019-01163-5","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"value":"0278-081X","type":"print"},{"value":"1531-5878","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,6,11]]},"assertion":[{"value":"22 June 2018","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"22 May 2019","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"24 May 2019","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"11 June 2019","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}