{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,26]],"date-time":"2025-11-26T16:32:16Z","timestamp":1764174736310,"version":"3.37.3"},"reference-count":31,"publisher":"Springer Science and Business Media LLC","issue":"6","license":[{"start":{"date-parts":[[2019,11,11]],"date-time":"2019-11-11T00:00:00Z","timestamp":1573430400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2019,11,11]],"date-time":"2019-11-11T00:00:00Z","timestamp":1573430400000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["U1613215"],"award-info":[{"award-number":["U1613215"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Shenzhen Science and Technology Innovation Committe","award":["JCYJ20170412150411676"],"award-info":[{"award-number":["JCYJ20170412150411676"]}]},{"name":"TSV 3D Integrated Micro\/Nano system Lab","award":["ZDSYS201802061805105"],"award-info":[{"award-number":["ZDSYS201802061805105"]}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Circuits Syst Signal Process"],"published-print":{"date-parts":[[2020,6]]},"DOI":"10.1007\/s00034-019-01300-0","type":"journal-article","created":{"date-parts":[[2019,11,11]],"date-time":"2019-11-11T19:02:46Z","timestamp":1573498966000},"page":"2822-2840","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":11,"title":["Design of High-Speed Logic Circuits with Four-Step RRAM-Based Logic Gates"],"prefix":"10.1007","volume":"39","author":[{"given":"Xiaole","family":"Cui","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiao","family":"Ma","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qiujun","family":"Lin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiang","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hang","family":"Zhou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0394-8839","authenticated-orcid":false,"given":"Xiaoxin","family":"Cui","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2019,11,11]]},"reference":[{"key":"1300_CR1","doi-asserted-by":"publisher","first-page":"873","DOI":"10.1038\/nature08940","volume":"464","author":"J Borghetti","year":"2010","unstructured":"J. Borghetti, G.S. Snider, \u2018Memristive\u2019 switch enable \u2018stateful\u2019 logic operations via material implication. Nature 464, 873\u2013876 (2010)","journal-title":"Nature"},{"key":"1300_CR2","unstructured":"Berkeley Logic Synthesis and Verification Group, ABC: a system for sequential synthesis and verification. http:\/\/www.eecs.berkeley.edu\/~alanmi\/abc\/. Accessed 8 Nov 2019"},{"key":"1300_CR3","unstructured":"J. B\u00fcrger, C. Teuscher, M. Perkowski, Digital logic synthesis for memristors, in Proceedings of the Reed-Muller Workshop (2013), pp. 1\u201310"},{"key":"1300_CR4","doi-asserted-by":"crossref","unstructured":"A. Chen, Comprehensive assessment of RRAM-based PUF for hardware security applications, in IEEE International Electron Devices Meeting, Washington DC USA (2015)","DOI":"10.1109\/IEDM.2015.7409672"},{"key":"1300_CR5","doi-asserted-by":"publisher","first-page":"115","DOI":"10.1109\/TNANO.2013.2241075","volume":"12","author":"L Gao","year":"2013","unstructured":"L. Gao, F. Alibart, Programmable CMOS\/memristor threshold logic. IEEE Trans. Nanotechnol. 12, 115\u2013119 (2013)","journal-title":"IEEE Trans. Nanotechnol."},{"key":"1300_CR6","doi-asserted-by":"publisher","first-page":"171","DOI":"10.1109\/TCSII.2016.2551554","volume":"64","author":"L Guckert","year":"2017","unstructured":"L. Guckert, E.E. Swartzlander, MAD gates- memristor logic design using driver circuitry. IEEE Trans. Circuits Syst. II Express Briefs. 64, 171\u2013175 (2017)","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs."},{"key":"1300_CR7","doi-asserted-by":"publisher","first-page":"373","DOI":"10.1109\/TCSI.2016.2606433","volume":"64","author":"L Guckert","year":"2017","unstructured":"L. Guckert, E.E. Swartzlander, Optimized memristor-based multipliers. IEEE Trans. Circuits Syst. I Regul. Pap. 64, 373\u2013385 (2017)","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"1300_CR8","doi-asserted-by":"publisher","first-page":"9758","DOI":"10.1002\/adma.201602418","volume":"28","author":"P Huang","year":"2016","unstructured":"P. Huang, J. Kang, Reconfigurable nonvolatile logic operations in resistance switching crossbar array for large-scale circuits. Adv. Mater. 28, 9758\u20139764 (2016)","journal-title":"Adv. Mater."},{"key":"1300_CR9","unstructured":"R.B. Hur, S. Kvatinsky, Memory processing unit for in-memory processing, in IEEE\/ACM International Symposium on Nanoscale Architecture (NANOARCH) (Beijing, 2016), pp. 171\u2013172"},{"key":"1300_CR10","doi-asserted-by":"crossref","unstructured":"R.B. Hur, N. Wald, Simple magic: synthesis and in-memory mapping of logic execution for memristor-aided logic, in IEEE\/ACM International Conference on Computer-Aided Design (ICCAD) (Irvine, 2017), pp. 225\u2013232","DOI":"10.1109\/ICCAD.2017.8203782"},{"key":"1300_CR11","doi-asserted-by":"crossref","unstructured":"A. Haj-Ali, R. Ben-Hur, Efficient algorithms for in-memory fixed point multiplication using MAGIC, in IEEE International Symposium on Circuits and Systems (ISCAS), (Florence, 2018), pp. 1\u20135","DOI":"10.1109\/ISCAS.2018.8351561"},{"key":"1300_CR12","unstructured":"S. Kvatinsky, N. Wald, MRL-memristorratioed logic, in IEEE International Workshop on Cellular Nanascale Networks and Their Applications (Turin, 2012), pp. 1\u20136"},{"key":"1300_CR13","doi-asserted-by":"publisher","first-page":"895","DOI":"10.1109\/TCSII.2014.2357292","volume":"61","author":"S Kvatinsky","year":"2014","unstructured":"S. Kvatinsky, D. Belousov, MAGIC-memristor-aided logic. IEEE Trans. Circuits Syst II Express Briefs. 61, 895\u2013899 (2014)","journal-title":"IEEE Trans. Circuits Syst II Express Briefs."},{"key":"1300_CR14","doi-asserted-by":"publisher","first-page":"2054","DOI":"10.1109\/TVLSI.2013.2282132","volume":"22","author":"S Kvatinsky","year":"2014","unstructured":"S. Kvatinsky, G. Satat, Memristor-based material implication (IMPLY) logic: design principles and methodologies. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22, 2054\u20132066 (2014)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"1","key":"1300_CR15","doi-asserted-by":"publisher","first-page":"13330","DOI":"10.1038\/srep13330","volume":"5","author":"H Li","year":"2015","unstructured":"H. Li, B. Gao, Z. Chen, A learnable parallel processing architecture towards unity of memory and computing. Scientific Rep. 5(1), 13330 (2015)","journal-title":"Scientific Rep."},{"key":"1300_CR16","doi-asserted-by":"crossref","unstructured":"F. Lalchhandama, B. Gopal, An improved approach for the synthesis of Boolean functions using memristor based IMPLY and INVERSE-IMPLY gates, in IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (Pittsburgh, 2016), pp. 319\u2013324","DOI":"10.1109\/ISVLSI.2016.61"},{"key":"1300_CR17","doi-asserted-by":"publisher","first-page":"211","DOI":"10.1109\/LED.2013.2293354","volume":"35","author":"H Li","year":"2014","unstructured":"H. Li, P. Huang, A SPICE model of resistive random access memory for large-scale memory array simulation. IEEE Electron Device Lett. 35, 211\u2013213 (2014)","journal-title":"IEEE Electron Device Lett."},{"key":"1300_CR18","doi-asserted-by":"publisher","first-page":"710","DOI":"10.1109\/LED.2011.2127439","volume":"32","author":"R Rosezin","year":"2011","unstructured":"R. Rosezin, E. Linn, Crossbar logic using bipolar and complementary resistive switches. IEEE Electron Device Lett. 32, 710\u2013712 (2011)","journal-title":"IEEE Electron Device Lett."},{"key":"1300_CR19","doi-asserted-by":"publisher","first-page":"2033","DOI":"10.1109\/JPROC.2011.2167489","volume":"100","author":"GS Rose","year":"2012","unstructured":"G.S. Rose, J. Rajendran, Leveraging memristive systems in the construction of digital logic circuits. Proc. IEEE. 100, 2033\u20132049 (2012)","journal-title":"Proc. IEEE."},{"key":"1300_CR20","unstructured":"Ragjivamsjo, A., Perkowski, M., Logic synthesis and a generalized notation for memristor-realized material implication gates, in IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), (San Jose, 2014), pp. 470\u2013477"},{"key":"1300_CR21","doi-asserted-by":"crossref","unstructured":"Sasi, A., Amirsoleimani, A., Hybrid memristor-CMOS based linear feedback shift register design, in IEEE International Conference on Electronics, Circuits and Systems (ICECS), (Batumi, 2017), pp. 62\u201365","DOI":"10.1109\/ICECS.2017.8292094"},{"key":"1300_CR22","doi-asserted-by":"crossref","unstructured":"P.L. Thangkhiew, R. Gharpinde, Area efficient implementation of ripple carry adder using memristorcorssbar array, in IEEE International Symposium on Design & Test (IDT) (Hammanet, 2016), pp. 142\u2013147","DOI":"10.1109\/IDT.2016.7843030"},{"key":"1300_CR23","doi-asserted-by":"publisher","first-page":"2466","DOI":"10.1109\/TCSI.2018.2792474","volume":"65","author":"PL Thangkhiew","year":"2018","unstructured":"P.L. Thangkhiew, R. Gharpinde, Efficient mapping of Boolean functions to memristor crossbar using MAGIC NOR gates. IEEE Trans. Circuits Syst I Regul. Pap. 65, 2466\u20132476 (2018)","journal-title":"IEEE Trans. Circuits Syst I Regul. Pap."},{"key":"1300_CR24","doi-asserted-by":"crossref","unstructured":"M. Teimoory, A. Amirsoleimani, Memristor-based linear feedback shift register based on material implication logic, in IEEE European Conference on Circuit Theory and Design, (Trondheim, 2015), pp. 1\u20134","DOI":"10.1109\/ECCTD.2015.7300100"},{"key":"1300_CR25","doi-asserted-by":"publisher","first-page":"1151","DOI":"10.1109\/TNANO.2012.2217153","volume":"11","author":"I Vourkas","year":"2012","unstructured":"I. Vourkas, G.C. Sirakoulis, A novel design and modeling paradigm for memristor-based crossbar circuits. IEEE Trans. Nanotechnol. 11, 1151\u20131159 (2012)","journal-title":"IEEE Trans. Nanotechnol."},{"key":"1300_CR26","unstructured":"X. Wang, R. Tan, Synthesis of memristive circuits based on stateful IMPLY gates using an evolutionary algorithm with a correction function, in IEEE\/ACM International Symposium on Nanoscale Architecture (NANOARCH) (Beijing, 2016), pp. 97\u2013102"},{"key":"1300_CR27","doi-asserted-by":"publisher","first-page":"2842","DOI":"10.1109\/TVLSI.2018.2816023","volume":"26","author":"HP Wang","year":"2018","unstructured":"H.P. Wang, C.C. Lin, On synthesizing memristor-based logic circuits with minimal operational pulses. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 26, 2842\u20132852 (2018)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"1300_CR28","doi-asserted-by":"publisher","first-page":"2641","DOI":"10.1109\/TVLSI.2018.2791625","volume":"26","author":"X Wang","year":"2018","unstructured":"X. Wang, S. Li, Configurable logic operations using hybrid CRS-CMOS cells. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 26, 2641\u20132647 (2018)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"1300_CR29","doi-asserted-by":"crossref","unstructured":"L. Xie, H.A. Du, Scouting logic: a novel memristor-based logic design for resistive computing, in IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (Bochum, 2017), pp. 176\u2013181","DOI":"10.1109\/ISVLSI.2017.39"},{"key":"1300_CR30","doi-asserted-by":"publisher","first-page":"94","DOI":"10.1109\/TNANO.2015.2504841","volume":"15","author":"Y Yang","year":"2016","unstructured":"Y. Yang, J. Mathew, Complementary resistive switch-based arithmetic logic implementations using material implication. IEEE Trans. Nanotechnol. 15, 94\u2013108 (2016)","journal-title":"IEEE Trans. Nanotechnol."},{"key":"1300_CR31","doi-asserted-by":"crossref","unstructured":"K. Zhang, X. Cui, A design of high performance full adder with memristors, in IEEE International Conference on ASIC (ASICON), (Guiyang, 2017), pp. 746\u2013749","DOI":"10.1109\/ASICON.2017.8252583"}],"container-title":["Circuits, Systems, and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-019-01300-0.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s00034-019-01300-0\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s00034-019-01300-0.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,10]],"date-time":"2020-11-10T00:16:20Z","timestamp":1604967380000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s00034-019-01300-0"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,11,11]]},"references-count":31,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2020,6]]}},"alternative-id":["1300"],"URL":"https:\/\/doi.org\/10.1007\/s00034-019-01300-0","relation":{},"ISSN":["0278-081X","1531-5878"],"issn-type":[{"type":"print","value":"0278-081X"},{"type":"electronic","value":"1531-5878"}],"subject":[],"published":{"date-parts":[[2019,11,11]]},"assertion":[{"value":"22 March 2019","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"27 October 2019","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"29 October 2019","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"11 November 2019","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}